The original sources of MS-DOS 1.25, 2.0, and 4.0 for reference purposes

A collection of the the best ML and AI news every week (research, news, resources)

Play DOOM in teletext

VGA to HDMI converter

A simple and flexible code for Reservoir Computing architectures like Echo State Networks

Demonstration of reservoir computing using a single dynamical node as described in: https://www.nature.com/articles/ncomms1476

A reading list for deep graph learning acceleration.

"Build it yourself" handheld game console based on the Raspberry Pi Pico microcontroller

MRAM magnetization simulation framework. s-LLGS python and verilog-a solvers for transients simulation and Fokker-planck equation solver for stochastic analysis

Transactional power-failsafe filesystem for microcontrollers

Two Level Segregated Fit (TLSF) memory allocator implementation, BSD License

For releasing code related to compression methods for transformers, accompanying our publications

This is originally a collection of papers on neural network accelerators. Now it's more like my selection of research on deep learning and computer architecture.

Implementation of the training framework proposed in Self-Rewarding Language Model, from MetaAI

The official JAX implementation of Mosaic paper

🔥 This repo collects top international conference papers, codes about Spiking Neural Networks. 本仓库收集了脉冲神经网络领域的顶会顶刊论文和代码，正在持续更新中。

A syllabic chording system for Plover, reminiscent of how the Veyboard and Velotype keyboards operate.

c64 assembly course

SGLang is a fast serving framework for large language models and vision language models.

Collection of Hyperdimensional Computing Projects

cocot46plus is a column staggered keyboard with 46 keys, a 34mm-trackball and a rotary encoder.

All my public C64 stuff

Commodore 64 VIC-II 6567/6569 Replacement Project

This repository contains the spreadsheet of the quantitative analysis performed for the paper "Suitability of Forward-Forward and PEPITA Learning to MLCommons-Tiny benchmarks".

Llama 2 Everywhere (L2E)

An implementation of the DLX RISC processor from RTL down to physical design