read_verilog/link_design support redirection

gongtonyhi · Jul 9, 2021 · 8c23d8e · 8c23d8e
1 parent c3624ed
commit 8c23d8e
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Showing 4 changed files with 13 additions and 3 deletions.
diff --git a/tcl/Link.tcl b/tcl/Link.tcl
@@ -20,9 +20,15 @@ namespace eval sta {
 
 define_cmd_args "link_design" {[top_cell_name]}
 
-proc link_design { {top_cell_name ""} } {
+proc_redirect link_design {
   variable current_design_name
 
+  check_argc_eq0or1 "link_design" $args
+  if { $args == "" } {
+    set top_cell_name ""
+  } else {
+    set top_cell_name [lindex $args 0]
+  }
   if { $top_cell_name == "" } {
     if { $current_design_name == "" } {
       sta_error 593 "missing top_cell_name argument and no current_design."

diff --git a/verilog/Verilog.i b/verilog/Verilog.i
@@ -31,7 +31,7 @@ using sta::readVerilogFile;
 %inline %{
 
 bool
-read_verilog(const char *filename)
+read_verilog_cmd(const char *filename)
 {
   Sta *sta = Sta::sta();
   NetworkReader *network = sta->networkReader();

diff --git a/verilog/Verilog.tcl b/verilog/Verilog.tcl
@@ -19,6 +19,10 @@ namespace eval sta {
 # Defined by SWIG interface Verilog.i.
 define_cmd_args "read_verilog" {filename}
 
+proc_redirect read_verilog {
+  read_verilog_cmd $args
+}
+
 define_cmd_args "write_verilog" {[-sort] [-include_pwr_gnd]\
 				   [-remove_cells cells] filename}
 

diff --git a/verilog/VerilogReader.cc b/verilog/VerilogReader.cc
@@ -1804,7 +1804,7 @@ VerilogReader::makeModuleInstNetwork(VerilogModuleInst *mod_inst,
     if (make_black_boxes) {
       cell = makeBlackBox(mod_inst, parent_module);
       linkWarn(198, filename_, mod_inst->line(),
-	       "module %s not found.  Creating black box for %s.",
+	       "module %s not found. Creating black box for %s.",
 	       mod_inst->moduleName(),
 	       verilogName(mod_inst));
     }