SystemC Reference Implementation

Verilog parser, preprocessor, and related tools for the Verilog-Perl package

VeeR EH1 core

The Ultra-Low Power RISC-V Core

The official repository for the gem5 computer-system architecture simulator.

How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design

The gem5 Bootcamp 2022 environment. Archived.

Vitis In-Depth Tutorials

Python on Zynq FPGA for Convolutional Neural Networks

A template project for beginning new Chisel work

Mill is a fast JVM build tool that supports Java, Scala, Kotlin and many other languages. 2-4x faster than Gradle and 4-10x faster than Maven for common workflows, Mill aims to make your project’s …

A Chisel RTL generator for network-on-chip interconnects

Learn make by example

SonicBOOM: The Berkeley Out-of-Order Machine

OpenXuantie - OpenC910 Core

CMurphi mirror: http://mclab.di.uniroma1.it/site/index.php/software/18-cmurphi

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

The batteries-included testing and formal verification library for Chisel-based RTL designs.

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

A minimal, modularized, and machine-independent hardware abstraction layer

RISC-V Instruction Set Manual

NJU EMUlator, a full system x86/mips32/riscv32/riscv64 emulator for teaching

Re0：从零开始的异世界生活 （WEB版）