Commits

Breadcrumbs

History for

onmain

User selector

All users

Datepicker

All time

Commit History

Commits on Dec 30, 2022

• minimax: complete Verilog rewrite

  Show description for 230e97d
  xobs

  committed
  230e97d

  Copy full SHA for 230e97d

• mimax: finish aluA, aluB, addrS, and addrD

  Show description for 96cde6e
  xobs

  committed
  96cde6e

  Copy full SHA for 96cde6e

• verilog: simplify concatenation logic

  Show description for fba8ce2
  xobs

  committed
  fba8ce2

  Copy full SHA for fba8ce2

• datapath: finish wiring up data path

  Show description for 0a48bc6
  xobs

  committed
  0a48bc6

  Copy full SHA for 0a48bc6

• fetch: complete fetch function

  Show description for 072e871
  xobs

  committed
  072e871

  Copy full SHA for 072e871

• trap: wire up trap signals

  Show description for b548e0c
  xobs

  committed
  b548e0c

  Copy full SHA for b548e0c

• decoder: finish rewriting instruction decoder

  Show description for 70b9968
  xobs

  committed
  70b9968

  Copy full SHA for 70b9968

• begin work on cleaning up generated Verilog

  Show description for 76b3640
  xobs

  committed
  76b3640

  Copy full SHA for 76b3640

Commits on Nov 16, 2022

• Losing custom SWAP operation is another 10% LUT diet. Worth it.

  gsmecher

  committed
  9f33cca

  Copy full SHA for 9f33cca

Commits on Nov 11, 2022

• Removes directly-implemented RV32I instructions from Minimax, in favour of emulated versions.

  Show description for e26496a
  gsmecher

  committed
  e26496a

  Copy full SHA for e26496a

Commits on Nov 4, 2022

• Adds a "blinker" reference design, directly usable on the ExaNIC X10.

  Show description for b4cbabd
  gsmecher

  committed
  b4cbabd

  Copy full SHA for b4cbabd

• Simplify ALU output multiplexing.

  Show description for 9de879a
  gsmecher

  committed
  9de879a

  Copy full SHA for 9de879a

Commits on Nov 3, 2022

• Don't run C.BEQZ/C.BNEZ checks through the ALU.

  Show description for 7fedc11
  gsmecher

  committed
  7fedc11

  Copy full SHA for 7fedc11

• Remove redundant logic in jump qualification.

  gsmecher

  committed
  86d0293

  Copy full SHA for 86d0293

• Combine rs_reg/rd_reg into single deferred-register-address (dra) reg.

  Show description for 031140e
  gsmecher

  committed
  031140e

  Copy full SHA for 031140e

Commits on Oct 28, 2022

• Remove duplicated documentation - now lives in README.md

  gsmecher

  committed
  8e51445

  Copy full SHA for 8e51445

• Removes multi-cycle shifts in favour of emulation.

  Show description for bfdcdb9
  gsmecher

  committed
  bfdcdb9

  Copy full SHA for bfdcdb9

• Vivado: Squash synthesis errors on simulation-only (trace) code.

  gsmecher

  committed
  db52c09

  Copy full SHA for db52c09

Commits on Oct 27, 2022

• Shifts regression tests to use ghdl by default, via FuseSoC.

  gsmecher

  committed
  22eba43

  Copy full SHA for 22eba43

• Generates trace in CPU core, not in testbench.

  Show description for 73dcc5b
  gsmecher

  committed
  73dcc5b

  Copy full SHA for 73dcc5b

• Make testbench portable beyond Xilinx xsim.

  Show description for ddfb80e
  gsmecher

  committed
  ddfb80e

  Copy full SHA for ddfb80e

Commits on Oct 26, 2022

• Initial commit of riscv-based minimax design.

  gsmecher

  committed
  c9d8a59

  Copy full SHA for c9d8a59

Loading

Pagination

Previous

Next