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Commits on Jul 10, 2023

• Complete deprecation of VHDL core.

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Commits on Apr 7, 2023

• Capture 3-stage pipelined design at a reasonable working stage.

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• We now close timing at 100 MHz on Artix-7.

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• First cut at FDE-pipelined Minimax. Passes tests.

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Commits on Apr 2, 2023

• Continue split between fetch and decode.

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• Remove 1 register stage from instruction RAM; dump it in core RTL.

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Commits on Mar 30, 2023

• Move half/byte write path to use shifter, not separate permuation mux.

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• Only trap on 32-bit instructions (16-bit check no longer relevant.)

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• Move to single full-shifter for c.srli/c.srai/c.slli

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• Captures naive 1-cycle-shift implementation. Passes test cases; costs ~200 LUTs.

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Commits on Mar 7, 2023

• Verilator lint: string constant length in TRACE_ENABLE fixture.

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Commits on Feb 28, 2023

• Switch RISCOF tests to verilator. Requires Verilator 5+.

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Commits on Jan 26, 2023

• Moves c.sb/c.sh shifter into regP network, which might be useful later.

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Commits on Jan 25, 2023

• Register data-bus reads and writes, and allow variable data-bus latency.

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• Shifts synthesis build to Arty A7.

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• Implement Zcb subset sufficient to emulate 32-bit SB/SH. Stub CSR opcodes.

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Commits on Jan 24, 2023

• Crash-land RISCOF compliance suite.

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Commits on Jan 23, 2023

• smarter bin2hex. This replaces bin2mem and is intended inject microcode.

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Commits on Jan 7, 2023

• minimax: add decoded instruction to trace output

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Commits on Jan 4, 2023

• minimax: use Verilog defines to disable $display

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Commits on Jan 3, 2023

• tb: implement working Verilog testbench

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• minimax: implement compatible tracing

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• minimax: agu: fix address generation unit

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• minimax: fixup formatting on assert statement

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• compare-reference: add more methods of comparing

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Commits on Jan 2, 2023

• minimax: minor cleanups in verilog code

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Commits on Jan 1, 2023

• minimax: add trace functionality

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• minimax: minor reformatting

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• minimax_tb: the test bench seems to work

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• minimax: move register wires to the bottom

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• minimax: wip: implement UC_BASE and PC_BITS

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• rtl: add testbench

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Commits on Dec 30, 2022

• compare: fix path to base file

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• rtl: clean up comments some more

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• minimax: begin to add parameters

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