sys-devel/llvm: Disable RISCV following upstream

The RISCV target is experimental and was only accidentally added to the main target list. Since it can no longer be enabled the usual way, remove it from the ebuilds for now.
hanetzer · Aug 15, 2017 · 22c9919 · 22c9919
1 parent 74f8341
commit 22c9919
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diff --git a/sys-devel/llvm/llvm-5.0.9999.ebuild b/sys-devel/llvm/llvm-5.0.9999.ebuild
@@ -20,7 +20,7 @@ EGIT_BRANCH="release_50"
 
 # Keep in sync with CMakeLists.txt
 ALL_LLVM_TARGETS=( AArch64 AMDGPU ARM BPF Hexagon Lanai Mips MSP430
- NVPTX PowerPC RISCV Sparc SystemZ X86 XCore )
+ NVPTX PowerPC Sparc SystemZ X86 XCore )
 ALL_LLVM_TARGETS=( "${ALL_LLVM_TARGETS[@]/#/llvm_targets_}" )
 
 # Additional licenses:

diff --git a/sys-devel/llvm/llvm-9999.ebuild b/sys-devel/llvm/llvm-9999.ebuild
@@ -19,7 +19,7 @@ EGIT_REPO_URI="https://git.llvm.org/git/llvm.git
 
 # Keep in sync with CMakeLists.txt
 ALL_LLVM_TARGETS=( AArch64 AMDGPU ARM BPF Hexagon Lanai Mips MSP430
- NVPTX PowerPC RISCV Sparc SystemZ X86 XCore )
+ NVPTX PowerPC Sparc SystemZ X86 XCore )
 ALL_LLVM_TARGETS=( "${ALL_LLVM_TARGETS[@]/#/llvm_targets_}" )
 
 # Additional licenses: