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Merge tag 'imx-dt64-5.19' of git://git.kernel.org/pub/scm/linux/kerne…
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…l/git/shawnguo/linux into arm/dt

i.MX arm64 device tree update for 5.19:

- New board support: Engicam i.Core MX8M Plus SoM and EDIMM2.2 Starter
  Kit, Toradex Verdin i.MX8M Plus devices, Data Modul i.MX8M Mini eDM SBC,
  Verdin based MX8Menlo, 8MNANOD3L EVK, i.MX8M Plus Gateworks GW7400.
- Enable RTS-CTS on UART3 for imx8mm-beacon and imx8mn-beacon boards.
- Enable HS400-ES support for i.MX8MN and i.MX8MP uSDHC devices by
  updating the compatible.
- A few updates on imx8mq-librem5 to increase boost regulation
  current, add panel compatible for r4 ("Evergreen") revision and volume
  buttons a wakeup source.
- Clean up vendor specific 'fsl,uart-has-rtscts' property by using
  standard 'uart-has-rtscts'.
- Add GPC, GPU, MEDIAMIX, and HSIO power domains for i.MX8M Plus SoC.
- A series from Marcel Ziswiler to improve imx8mm-verdin support,
  including cosmetic changes and functional improvements like SD1 sleep
  pinctrl and fully validated IOMUX configuration.
- Add PWM polarity inversion support for i.MX8 SoCs.
- A couple of changes from Michael Walle to update PMIC output names and
  min/max voltages for imx8mn-evk board.
- A series from Tim Harvey to improve imx8mm-venice boards, add missing
  uart-has-rtscts property to UARTs, clock-names to pcie_phy, and
  vdd_5p0 ADC channel.
- Add VPU codec  devices for i.MX8QXP SoC.
- Other small and random changes.

* tag 'imx-dt64-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (65 commits)
  arm64: dt: imx8mp: support pwm polarity inversion
  arm64: dt: imx8mn: support pwm polarity inversion
  arm64: dt: imx8mm: support pwm polarity inversion
  arm64: dt: imx8mq: support pwm polarity inversion
  arm64: dts: imx8mm-venice-gw7901: remove unnecessary cpu temp override
  arm64: dts: imx8mm-venice-gw7902: add vdd_5p0 ADC channel
  arm64: dts: imx8m*venice: add missing clock-names to pcie_phy
  arm64: dts: imx8mm-venice-gw7902: fix pcie bindings
  arm64: dts: freescale: reduce the interrup-map-mask
  arm64: dts: imx8mn-beacon: Enable RTS-CTS on UART3
  arm64: dts: imx8mm-beacon: Enable RTS-CTS on UART3
  arm64: dts: imx8mm: Use 100 kHz I2C2 on Data Modul i.MX8M Mini eDM SBC
  arm64: dts: imx8mm: Disable USB2 OC on Data Modul i.MX8M Mini eDM SBC
  arm64: dts: imx8mm: Add CPLD on MX8Menlo board
  arm64: dts: imx8mq-kontron-pitx-imx8m: Use the standard 'uart-has-rtscts'
  arm64: dts: imx8mp-verdin: Use the standard 'uart-has-rtscts'
  arm64: dts: imx8mp: Add MEDIA_BLK_CTRL
  arm64: dts: imx8mp: Add MEDIAMIX power domains
  arm64: dts: imx8mp: add HSIO power-domains
  arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit
  ...

Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Arnd Bergmann <[email protected]>
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arndb committed May 9, 2022
2 parents 31df43e + d80b9c8 commit 977389a
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Showing 58 changed files with 5,355 additions and 314 deletions.
9 changes: 9 additions & 0 deletions arch/arm64/boot/dts/freescale/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -49,12 +49,14 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-899b.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-9999.dtb

dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-data-modul-edm-sbc.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-emcon-avari.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-mx8menlo.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb
Expand All @@ -72,12 +74,19 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-beacon-kit.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2pro.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr3l-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dahlia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-dahlia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-kontron-pitx-imx8m.dtb
Expand Down
9 changes: 9 additions & 0 deletions arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts
Original file line number Diff line number Diff line change
Expand Up @@ -311,10 +311,19 @@
status = "okay";
};

&mscc_felix_port4 {
dsa-tag-protocol = "ocelot-8021q";
};

&mscc_felix_port5 {
dsa-tag-protocol = "ocelot-8021q";
};

&usb0 {
status = "okay";
};

&usb1 {
dr_mode = "host";
status = "okay";
};
2 changes: 2 additions & 0 deletions arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
Original file line number Diff line number Diff line change
Expand Up @@ -382,9 +382,11 @@
};

&usb0 {
dr_mode = "host";
status = "okay";
};

&usb1 {
dr_mode = "host";
status = "okay";
};
2 changes: 1 addition & 1 deletion arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
Original file line number Diff line number Diff line change
Expand Up @@ -299,10 +299,10 @@
};

&usb0 {
dr_mode = "host";
status = "okay";
};

&usb1 {
dr_mode = "otg";
status = "okay";
};
2 changes: 0 additions & 2 deletions arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -599,7 +599,6 @@
compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,dis_rxdet_inp3_quirk;
snps,quirk-frame-length-adjustment = <0x20>;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
Expand All @@ -610,7 +609,6 @@
compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
reg = <0x0 0x3110000 0x0 0x10000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
snps,dis_rxdet_inp3_quirk;
snps,quirk-frame-length-adjustment = <0x20>;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
Expand Down
6 changes: 3 additions & 3 deletions arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -335,7 +335,7 @@
<9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
<11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0xffffffff 0x0>;
interrupt-map-mask = <0xf 0x0>;
};
};

Expand Down Expand Up @@ -389,8 +389,8 @@
big-endian;
};

ifc: ifc@1530000 {
compatible = "fsl,ifc", "simple-bus";
ifc: memory-controller@1530000 {
compatible = "fsl,ifc";
reg = <0x0 0x1530000 0x0 0x10000>;
interrupts = <0 43 0x4>;
};
Expand Down
6 changes: 3 additions & 3 deletions arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -280,8 +280,8 @@
big-endian;
};

ifc: ifc@1530000 {
compatible = "fsl,ifc", "simple-bus";
ifc: memory-controller@1530000 {
compatible = "fsl,ifc";
reg = <0x0 0x1530000 0x0 0x10000>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
Expand Down Expand Up @@ -341,7 +341,7 @@
<9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
<11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0xffffffff 0x0>;
interrupt-map-mask = <0xf 0x0>;
};
};

Expand Down
6 changes: 3 additions & 3 deletions arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -265,7 +265,7 @@
<9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0xffffffff 0x0>;
interrupt-map-mask = <0xf 0x0>;
};
};

Expand Down Expand Up @@ -396,8 +396,8 @@
#interrupt-cells = <2>;
};

ifc: ifc@2240000 {
compatible = "fsl,ifc", "simple-bus";
ifc: memory-controller@2240000 {
compatible = "fsl,ifc";
reg = <0x0 0x2240000 0x0 0x20000>;
interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
little-endian;
Expand Down
10 changes: 5 additions & 5 deletions arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -104,21 +104,21 @@

&dspi {
status = "okay";
dflash0: n25q128a@0 {
dflash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
spi-max-frequency = <3000000>;
reg = <0>;
};
dflash1: sst25wf040b@1 {
dflash1: flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
spi-max-frequency = <3000000>;
reg = <1>;
};
dflash2: en25s64@2 {
dflash2: flash@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
Expand All @@ -129,7 +129,7 @@

&qspi {
status = "okay";
flash0: s25fl256s1@0 {
flash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
Expand All @@ -138,7 +138,7 @@
spi-tx-bus-width = <4>;
reg = <0>;
};
flash2: s25fl256s1@2 {
flash2: flash@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
Expand Down
2 changes: 1 addition & 1 deletion arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -100,7 +100,7 @@

&dspi {
status = "okay";
dflash0: n25q512a@0 {
dflash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
Expand Down
6 changes: 3 additions & 3 deletions arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -305,7 +305,7 @@
<9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0xffffffff 0x0>;
interrupt-map-mask = <0xf 0x0>;
};
};

Expand Down Expand Up @@ -1036,8 +1036,8 @@
QORIQ_CLK_PLL_DIV(4)>;
};

ifc: ifc@2240000 {
compatible = "fsl,ifc", "simple-bus";
ifc: memory-controller@2240000 {
compatible = "fsl,ifc";
reg = <0x0 0x2240000 0x0 0x20000>;
interrupts = <0 21 0x4>; /* Level high type */
little-endian;
Expand Down
6 changes: 3 additions & 3 deletions arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -698,7 +698,7 @@
<9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0xffffffff 0x0>;
interrupt-map-mask = <0xf 0x0>;
};
};

Expand Down Expand Up @@ -909,7 +909,7 @@
QORIQ_CLK_PLL_DIV(8)>,
<&clockgen QORIQ_CLK_SYSCLK 0>;
clock-names = "ipg", "per";
fsl,clk-source = <0>;
fsl,clk-source = /bits/ 8 <0>;
status = "disabled";
};

Expand All @@ -921,7 +921,7 @@
QORIQ_CLK_PLL_DIV(8)>,
<&clockgen QORIQ_CLK_SYSCLK 0>;
clock-names = "ipg", "per";
fsl,clk-source = <0>;
fsl,clk-source = /bits/ 8 <0>;
status = "disabled";
};

Expand Down
74 changes: 74 additions & 0 deletions arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi
Original file line number Diff line number Diff line change
@@ -0,0 +1,74 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 NXP
* Dong Aisheng <[email protected]>
*/

vpu: vpu@2c000000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x2c000000 0x0 0x2c000000 0x2000000>;
reg = <0 0x2c000000 0 0x1000000>;
power-domains = <&pd IMX_SC_R_VPU>;
status = "disabled";

mu_m0: mailbox@2d000000 {
compatible = "fsl,imx6sx-mu";
reg = <0x2d000000 0x20000>;
interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
power-domains = <&pd IMX_SC_R_VPU_MU_0>;
status = "disabled";
};

mu1_m0: mailbox@2d020000 {
compatible = "fsl,imx6sx-mu";
reg = <0x2d020000 0x20000>;
interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
power-domains = <&pd IMX_SC_R_VPU_MU_1>;
status = "disabled";
};

mu2_m0: mailbox@2d040000 {
compatible = "fsl,imx6sx-mu";
reg = <0x2d040000 0x20000>;
interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <2>;
power-domains = <&pd IMX_SC_R_VPU_MU_2>;
status = "disabled";
};

vpu_core0: vpu-core@2d080000 {
reg = <0x2d080000 0x10000>;
compatible = "nxp,imx8q-vpu-decoder";
power-domains = <&pd IMX_SC_R_VPU_DEC_0>;
mbox-names = "tx0", "tx1", "rx";
mboxes = <&mu_m0 0 0>,
<&mu_m0 0 1>,
<&mu_m0 1 0>;
status = "disabled";
};

vpu_core1: vpu-core@2d090000 {
reg = <0x2d090000 0x10000>;
compatible = "nxp,imx8q-vpu-encoder";
power-domains = <&pd IMX_SC_R_VPU_ENC_0>;
mbox-names = "tx0", "tx1", "rx";
mboxes = <&mu1_m0 0 0>,
<&mu1_m0 0 1>,
<&mu1_m0 1 0>;
status = "disabled";
};

vpu_core2: vpu-core@2d0a0000 {
reg = <0x2d0a0000 0x10000>;
compatible = "nxp,imx8q-vpu-encoder";
power-domains = <&pd IMX_SC_R_VPU_ENC_1>;
mbox-names = "tx0", "tx1", "rx";
mboxes = <&mu2_m0 0 0>,
<&mu2_m0 0 1>,
<&mu2_m0 1 0>;
status = "disabled";
};
};
3 changes: 3 additions & 0 deletions arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -278,6 +278,7 @@
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MM_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
};

Expand Down Expand Up @@ -386,6 +387,8 @@
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40
MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40
MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x40
MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x40
>;
};

Expand Down
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