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Merge tag 'imx-dt64-5.19' of git://git.kernel.org/pub/scm/linux/kerne…
…l/git/shawnguo/linux into arm/dt i.MX arm64 device tree update for 5.19: - New board support: Engicam i.Core MX8M Plus SoM and EDIMM2.2 Starter Kit, Toradex Verdin i.MX8M Plus devices, Data Modul i.MX8M Mini eDM SBC, Verdin based MX8Menlo, 8MNANOD3L EVK, i.MX8M Plus Gateworks GW7400. - Enable RTS-CTS on UART3 for imx8mm-beacon and imx8mn-beacon boards. - Enable HS400-ES support for i.MX8MN and i.MX8MP uSDHC devices by updating the compatible. - A few updates on imx8mq-librem5 to increase boost regulation current, add panel compatible for r4 ("Evergreen") revision and volume buttons a wakeup source. - Clean up vendor specific 'fsl,uart-has-rtscts' property by using standard 'uart-has-rtscts'. - Add GPC, GPU, MEDIAMIX, and HSIO power domains for i.MX8M Plus SoC. - A series from Marcel Ziswiler to improve imx8mm-verdin support, including cosmetic changes and functional improvements like SD1 sleep pinctrl and fully validated IOMUX configuration. - Add PWM polarity inversion support for i.MX8 SoCs. - A couple of changes from Michael Walle to update PMIC output names and min/max voltages for imx8mn-evk board. - A series from Tim Harvey to improve imx8mm-venice boards, add missing uart-has-rtscts property to UARTs, clock-names to pcie_phy, and vdd_5p0 ADC channel. - Add VPU codec devices for i.MX8QXP SoC. - Other small and random changes. * tag 'imx-dt64-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (65 commits) arm64: dt: imx8mp: support pwm polarity inversion arm64: dt: imx8mn: support pwm polarity inversion arm64: dt: imx8mm: support pwm polarity inversion arm64: dt: imx8mq: support pwm polarity inversion arm64: dts: imx8mm-venice-gw7901: remove unnecessary cpu temp override arm64: dts: imx8mm-venice-gw7902: add vdd_5p0 ADC channel arm64: dts: imx8m*venice: add missing clock-names to pcie_phy arm64: dts: imx8mm-venice-gw7902: fix pcie bindings arm64: dts: freescale: reduce the interrup-map-mask arm64: dts: imx8mn-beacon: Enable RTS-CTS on UART3 arm64: dts: imx8mm-beacon: Enable RTS-CTS on UART3 arm64: dts: imx8mm: Use 100 kHz I2C2 on Data Modul i.MX8M Mini eDM SBC arm64: dts: imx8mm: Disable USB2 OC on Data Modul i.MX8M Mini eDM SBC arm64: dts: imx8mm: Add CPLD on MX8Menlo board arm64: dts: imx8mq-kontron-pitx-imx8m: Use the standard 'uart-has-rtscts' arm64: dts: imx8mp-verdin: Use the standard 'uart-has-rtscts' arm64: dts: imx8mp: Add MEDIA_BLK_CTRL arm64: dts: imx8mp: Add MEDIAMIX power domains arm64: dts: imx8mp: add HSIO power-domains arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit ... Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
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&usb0 { | ||
dr_mode = "host"; | ||
status = "okay"; | ||
}; | ||
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&usb1 { | ||
dr_mode = "host"; | ||
status = "okay"; | ||
}; |
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}; | ||
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&usb0 { | ||
dr_mode = "host"; | ||
status = "okay"; | ||
}; | ||
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&usb1 { | ||
dr_mode = "otg"; | ||
status = "okay"; | ||
}; |
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// SPDX-License-Identifier: GPL-2.0+ | ||
/* | ||
* Copyright 2021 NXP | ||
* Dong Aisheng <[email protected]> | ||
*/ | ||
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vpu: vpu@2c000000 { | ||
#address-cells = <1>; | ||
#size-cells = <1>; | ||
ranges = <0x2c000000 0x0 0x2c000000 0x2000000>; | ||
reg = <0 0x2c000000 0 0x1000000>; | ||
power-domains = <&pd IMX_SC_R_VPU>; | ||
status = "disabled"; | ||
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mu_m0: mailbox@2d000000 { | ||
compatible = "fsl,imx6sx-mu"; | ||
reg = <0x2d000000 0x20000>; | ||
interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; | ||
#mbox-cells = <2>; | ||
power-domains = <&pd IMX_SC_R_VPU_MU_0>; | ||
status = "disabled"; | ||
}; | ||
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||
mu1_m0: mailbox@2d020000 { | ||
compatible = "fsl,imx6sx-mu"; | ||
reg = <0x2d020000 0x20000>; | ||
interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; | ||
#mbox-cells = <2>; | ||
power-domains = <&pd IMX_SC_R_VPU_MU_1>; | ||
status = "disabled"; | ||
}; | ||
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mu2_m0: mailbox@2d040000 { | ||
compatible = "fsl,imx6sx-mu"; | ||
reg = <0x2d040000 0x20000>; | ||
interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; | ||
#mbox-cells = <2>; | ||
power-domains = <&pd IMX_SC_R_VPU_MU_2>; | ||
status = "disabled"; | ||
}; | ||
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vpu_core0: vpu-core@2d080000 { | ||
reg = <0x2d080000 0x10000>; | ||
compatible = "nxp,imx8q-vpu-decoder"; | ||
power-domains = <&pd IMX_SC_R_VPU_DEC_0>; | ||
mbox-names = "tx0", "tx1", "rx"; | ||
mboxes = <&mu_m0 0 0>, | ||
<&mu_m0 0 1>, | ||
<&mu_m0 1 0>; | ||
status = "disabled"; | ||
}; | ||
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vpu_core1: vpu-core@2d090000 { | ||
reg = <0x2d090000 0x10000>; | ||
compatible = "nxp,imx8q-vpu-encoder"; | ||
power-domains = <&pd IMX_SC_R_VPU_ENC_0>; | ||
mbox-names = "tx0", "tx1", "rx"; | ||
mboxes = <&mu1_m0 0 0>, | ||
<&mu1_m0 0 1>, | ||
<&mu1_m0 1 0>; | ||
status = "disabled"; | ||
}; | ||
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vpu_core2: vpu-core@2d0a0000 { | ||
reg = <0x2d0a0000 0x10000>; | ||
compatible = "nxp,imx8q-vpu-encoder"; | ||
power-domains = <&pd IMX_SC_R_VPU_ENC_1>; | ||
mbox-names = "tx0", "tx1", "rx"; | ||
mboxes = <&mu2_m0 0 0>, | ||
<&mu2_m0 0 1>, | ||
<&mu2_m0 1 0>; | ||
status = "disabled"; | ||
}; | ||
}; |
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