add 1 to reset

hdl-util · Mar 1, 2021 · 510f791 · 510f791
1 parent 46bde8e
commit 510f791
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Showing 2 changed files with 5 additions and 3 deletions.
diff --git a/src/unipolar_rz.sv b/src/unipolar_rz.sv
@@ -25,7 +25,7 @@ module unipolar_rz #(
     output logic ready
 );
 
-localparam int TIME_COUNTER_WIDTH = $clog2($unsigned(int'($unsigned(CLOCK_RATE) * (RESET_TIME + (ONE_LOW_TIME > ZERO_LOW_TIME ? ONE_LOW_TIME : ZERO_LOW_TIME)))));
+localparam int TIME_COUNTER_WIDTH = $clog2($unsigned(int'(1 + $unsigned(CLOCK_RATE) * (RESET_TIME + (ONE_LOW_TIME > ZERO_LOW_TIME ? ONE_LOW_TIME : ZERO_LOW_TIME)))));
 
 localparam bit [TIME_COUNTER_WIDTH-1:0] PERIOD = TIME_COUNTER_WIDTH'($unsigned(CLOCK_RATE) * PERIOD_TIME - 1);
 localparam bit [TIME_COUNTER_WIDTH-1:0] ZERO_LOW = TIME_COUNTER_WIDTH'($unsigned(CLOCK_RATE) * ZERO_LOW_TIME - 1);
@@ -84,7 +84,7 @@ begin
             begin
                 internal_data <= 1'bx;
                 state <= STATE_WIDTH'(0);
-                time_counter <= RESET + ((INVERT ? !internal_data[0] : internal_data[0]) ? ONE_LOW : ZERO_LOW);
+                time_counter <= RESET + ((INVERT ? !internal_data[0] : internal_data[0]) ? ONE_LOW : ZERO_LOW) + TIME_COUNTER_WIDTH'(1);
             end
         end
         else

diff --git a/test/sk6805_tb.sv b/test/sk6805_tb.sv
@@ -77,6 +77,7 @@ module sk6805_tb (
                 now = $realtime;
                 wait (!line);
                 high_time = $realtime - now;
+                now = $realtime;
                 if (high_time == 600)
                 begin
                     // one
@@ -94,7 +95,8 @@ module sk6805_tb (
             end
             current_data  = current_data + 1;
         end
-        wait(!line);
+        wait(ready && clock);
+        assert(($realtime - now) == 80190) else $fatal("did not reset");
         $finish;
     end
 endmodule