OpenTitan: Open source silicon root of trust

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

AMBA AXI VIP

4 stage, in-order, compute RISC-V core based on the CV32E40P

AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).

AMBA AHB 2.0 VIP in SystemVerilog UVM

VIP for AXI Protocol

UVM AHB VIP

An Open-Source Design and Verification Environment for RISC-V

SystemVerilog VIP for AMBA APB protocol

Verification IP for APB protocol

amba3 apb/axi vip

UVM APB VIP, part of AMBA3&AMBA4 feature supported

UVM VIP architecture generator

Register Agent

AMBA AHB 5.0 VIP in SystemVerilog based on UVM

AMBA AHB 2.0 VIP in SystemVerilog UVM

SV/UVM based instruction generator for RISC-V processor verification

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

UVM examples and projects

🍬UVM candy lover testbench which uses YASA as simulation script

OpenTitan: Open source silicon root of trust

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

Extensions to the UVM