AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).

Verilog AXI components for FPGA implementation

AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

VIP for AXI Protocol

AMBA AXI VIP

AMBA AHB 5.0 VIP in SystemVerilog based on UVM

AMBA AHB 2.0 VIP in SystemVerilog UVM

amba3 apb/axi vip

Verification IP for APB protocol

UVM AHB VIP

SystemVerilog VIP for AMBA APB protocol

UVM register utility generation by inputting xls table

UVM VIP architecture generator

UVM APB VIP, part of AMBA3&AMBA4 feature supported

Spike, a RISC-V ISA Simulator

Random instruction generator for RISC-V processor verification

An Open-Source Design and Verification Environment for RISC-V

4 stage, in-order, compute RISC-V core based on the CV32E40P

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Functional verification project for the CORE-V family of RISC-V cores.

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

A small, light weight, RISC CPU soft core

RISC-V CPU Core (RV32IM)

A very simple and easy to understand RISC-V core.

RTL, Cmodel, and testbench for NVDLA

IC design and development should be faster，simpler and more reliable