Update VEX support to r3206, useful for Intel MPX

But VEX's non-Valgrind Makefile is broken in this version, so a
patch for it is needed.

INSTALL

@@ -78,20 +78,28 @@ changes incompatibly from time to time, requiring matching updates in
 our interface code (look for "#if VEX_VERSION > xxxx" in
 libasmir/src).
 
-The most recent version of VEX we've checked to work correctly out of
-the box is r2737. Typical commands to check out and compile it look
-like:
+The most recent version of VEX we've tested with is r3206. However it
+doesn't work out of the box because the Valgrind developers have
+broken their Makefile. A patch for this is in vex-r3206.patch. You'll
+want to use this version if you're running x86-64 binaries new enough
+to contain MPX instructions, since VEX versions before r2858 can't
+deal with them. However ARM support hasn't been tested in this version
+yet.
+
+The more recent stable version of VEX we recommend is r2737. For x86
+and x86-64 it works out of the box. Typical commands to check out and
+compile it look like:
 
    % svn co -r2737 svn://svn.valgrind.org/vex/trunk vex-r2737
    % cd vex-r2737
    % make -f Makefile-gcc
 
-For many uses of FuzzBALL, especially on x86, any version of VEX will
-work just fine. If you want to run on ARM code it's more important to
-use a more recent version. Some changes to VEX to make it work better
-for our purposes are in vex-r????.patch. For x86, these only affect a
-few obscure instructions. But for ARM they also disable a Thumb
-instruction optimization that tries to peek directly at other
+For many uses of FuzzBALL, and especially on x86-32, any version of
+VEX will work just fine. If you want to run on ARM code it's more
+important to use a more recent version. Some changes to VEX to make it
+work better for our purposes are in vex-r????.patch. For x86, these
+only affect a few obscure instructions. But for ARM they also disable
+a Thumb instruction optimization that tries to peek directly at other
 instruction bytes in a way that usually crashes FuzzBALL.
 
 The oldest version we've traditionally used is r1856. Back then the

libasmir/src/vex/irtoir-arm.cpp

@@ -77,8 +77,15 @@
 #else
 #define OFFB_EMWARN        offsetof(VexGuestARMState,guest_EMNOTE)
 #endif
+
+#if VEX_VERSION < 2852
 #define OFFB_TISTART       offsetof(VexGuestARMState,guest_TISTART)
 #define OFFB_TILEN         offsetof(VexGuestARMState,guest_TILEN)
+#else
+#define OFFB_TISTART       offsetof(VexGuestARMState,guest_CMSTART)
+#define OFFB_TILEN         offsetof(VexGuestARMState,guest_CMLEN)
+#endif
+
 #define OFFB_NRADDR        offsetof(VexGuestARMState,guest_NRADDR)
 #define OFFB_IP_AT_SYSCALL offsetof(VexGuestARMState,guest_IP_AT_SYSCALL)
 #endif

libasmir/src/vex/irtoir-i386.cpp

@@ -90,8 +90,14 @@
 #define OFFB_EMWARN    offsetof(VexGuestX86State,guest_EMNOTE)
 #endif
 
+#if VEX_VERSION < 2852
 #define OFFB_TISTART   offsetof(VexGuestX86State,guest_TISTART)
 #define OFFB_TILEN     offsetof(VexGuestX86State,guest_TILEN)
+#else
+#define OFFB_TISTART   offsetof(VexGuestX86State,guest_CMSTART)
+#define OFFB_TILEN     offsetof(VexGuestX86State,guest_CMLEN)
+#endif
+
 #define OFFB_NRADDR    offsetof(VexGuestX86State,guest_NRADDR)
 #if VEX_VERSION >= 1536
 #define OFFB_SC_CLASS  offsetof(VexGuestX86State,guest_SC_CLASS)

libasmir/src/vex/irtoir-x64.cpp

@@ -37,8 +37,13 @@
 
 #define OFFB_RIP       offsetof(VexGuestAMD64State,guest_RIP)
 
-#define OFFB_FS_ZERO   offsetof(VexGuestAMD64State,guest_FS_ZERO)
-#define OFFB_GS_0x60   offsetof(VexGuestAMD64State,guest_GS_0x60)
+#if VEX_VERSION < 3043
+#define OFFB_FS_CONST   offsetof(VexGuestAMD64State,guest_FS_ZERO)
+#define OFFB_GS_CONST   offsetof(VexGuestAMD64State,guest_GS_0x60)
+#else
+#define OFFB_FS_CONST   offsetof(VexGuestAMD64State,guest_FS_CONST)
+#define OFFB_GS_CONST   offsetof(VexGuestAMD64State,guest_GS_CONST)
+#endif
 
 #define OFFB_CC_OP     offsetof(VexGuestAMD64State,guest_CC_OP)
 #define OFFB_CC_DEP1   offsetof(VexGuestAMD64State,guest_CC_DEP1)
@@ -211,8 +216,8 @@ vector<VarDecl *> x64_get_reg_decls()
   ret.push_back(new VarDecl("R_OF", r1));  
 
   // VEX represetations of segment information
-  ret.push_back(new VarDecl("R_FS_ZERO", r64));
-  ret.push_back(new VarDecl("R_GS_0x60", r64));
+  ret.push_back(new VarDecl("R_FS_CONST", r64));
+  ret.push_back(new VarDecl("R_GS_CONST", r64));
 
   // SIMD registers. We don't yet support 256-bit registers, so break
   // them up a 4x64. 
@@ -373,10 +378,10 @@ static string reg_offset_to_name( int offset, bool *is_good )
         case OFFB_NRADDR:   name = "NRADDR";    good=true; break;
 
 #if VEX_VERSION >= 919
-        case OFFB_FS_ZERO:  name = "FS_BASE";   good=true; break;
+        case OFFB_FS_CONST: name = "FS_BASE";   good=true; break;
 #endif
 #if VEX_VERSION >= 1874
-        case OFFB_GS_0x60:  name = "GS_BASE";   good=true; break;
+        case OFFB_GS_CONST: name = "GS_BASE";   good=true; break;
 #endif
 
         case OFFB_YMM0:     name = "YMM0_0";    good=true; break;

libasmir/src/vex/irtoir.cpp

@@ -2304,11 +2304,17 @@ Stmt *translate_jumpkind( IRSB *irbb, vector<Stmt *> *irout )
       Exp::destroy(dest);
       break;
 #endif
-#if VEX_VERSION >= 1320
+#if VEX_VERSION >= 1320 && VEX_VERSION < 2852
     case Ijk_TInval:
       irout->push_back( new Special("TInval") );
       result = new Jmp(dest);
       break; 
+#endif
+#if VEX_VERSION >= 2852
+    case Ijk_InvalICache:
+      irout->push_back( new Special("TInval") );
+      result = new Jmp(dest);
+      break;
 #endif
     default:
       assert(0);

libasmir/src/vex/vexir.cpp

@@ -105,7 +105,13 @@ FILE *change_vex_debug_out(FILE *new_fp) {
     return old_fp;
 }
 
-void log_bytes( HChar* bytes, Int nbytes )
+void log_bytes( const HChar* bytes,
+#if VEX_VERSION < 3047
+		Int nbytes
+#else
+		SizeT nbytes
+#endif
+		)
 {
     if (vex_debug_fp) {
 	fwrite(bytes, 1, nbytes, vex_debug_fp);
@@ -115,7 +121,13 @@ void log_bytes( HChar* bytes, Int nbytes )
     }
 }
 
-Bool chase_into_ok( void *closureV, Addr64 addr64 )
+Bool chase_into_ok( void *closureV,
+#if VEX_VERSION < 3050
+		    Addr64 addr
+#else
+		    Addr addr
+#endif
+		    )
 {
     return False;
 }
@@ -130,10 +142,10 @@ void *dispatch( void )
 //----------------------------------------------------------------------
 IRSB *instrument1(  void *callback_opaque, 
                     IRSB *irbb,
-                    VexGuestLayout *vgl,
-                    VexGuestExtents *vge,
+                    const VexGuestLayout *vgl,
+                    const VexGuestExtents *vge,
 #if VEX_VERSION >= 2549
-		    VexArchInfo *archinfo_host_unused,
+		    const VexArchInfo *archinfo_host_unused,
 #endif
                     IRType gWordTy,
                     IRType hWordTy )
@@ -180,7 +192,11 @@ int count_bb_insns( asm_bb_t *bb, asm_function_t *func )
 }
 
 #if VEX_VERSION >= 2158
-static UInt dont_need_self_check ( void* opaque, VexGuestExtents* vge ) {
+static UInt dont_need_self_check ( void* opaque,
+#if VEX_VERSION >= 3084
+				   VexRegisterUpdates* pxControl,
+#endif
+				   const VexGuestExtents* vge ) {
    return 0;
 }
 #endif
@@ -206,8 +222,10 @@ void translate_init()
     vc.iropt_level                  = 2;
 #if VEX_VERSION < 2454
     vc.iropt_precise_memory_exns    = False;
-#else
+#elsif VEX_VERSION < 3084
     vc.iropt_register_updates       = VexRegUpdUnwindregsAtMemAccess;
+#else
+    vc.iropt_register_updates_default=VexRegUpdUnwindregsAtMemAccess;
 #endif
     vc.iropt_unroll_thresh          = 0;
     vc.guest_max_insns              = 1;    // By default, we translate 1 instruction at a time
@@ -219,7 +237,9 @@ void translate_init()
     LibVEX_Init(&failure_exit, 
                 &log_bytes, 
                 0,              // Debug level
+#if VEX_VERSION < 2955
                 False,          // Valgrind support
+#endif
                 &vc );
 
     // Setup the translation args
@@ -233,6 +253,9 @@ void translate_init()
     case VexArchARM:   vai_host.hwcaps = ARM_HWCAPS;   break;
     default:           assert(0); /* unsupported arch. */
     }
+#if VEX_VERSION >= 2910
+    vai_host.endness = VexEndnessLE;
+#endif
     vta.archinfo_host       = vai_host;
     vta.guest_bytes         = NULL;             // Set in translate_insns
     vta.guest_bytes_addr    = 0;                // Set in translate_insns
@@ -306,6 +329,9 @@ IRSB *translate_insn( VexArch guest,
       break;
     default:           assert(0); /* unsupported arch. */
     }
+#if VEX_VERSION >= 2910
+    vai_guest.endness = VexEndnessLE;
+#endif
 
     vta.arch_guest = guest;
     vta.archinfo_guest = vai_guest;
@@ -330,11 +356,16 @@ IRSB *translate_insn( VexArch guest,
 
 #if VEX_VERSION >= 1875
       // Allow both %fs and %gs overrides. This doesn't really assume
-      // the partuclar values implied by the field names, just that we
-      // will always be able to get the base address out of the guest
-      // state.
+      // the partuclar values implied by the (original) field names,
+      // just that we will always be able to get the base address out
+      // of the guest state.
+#if VEX_VERSION < 3043
       vta.abiinfo_both.guest_amd64_assume_fs_is_zero = 1;
       vta.abiinfo_both.guest_amd64_assume_gs_is_0x60 = 1;
+#else
+      vta.abiinfo_both.guest_amd64_assume_fs_is_const = 1;
+      vta.abiinfo_both.guest_amd64_assume_gs_is_const = 1;
+#endif
 #endif
     }
 #endif

vex-r3206.patch

@@ -0,0 +1,138 @@
+Index: Makefile-gcc
+===================================================================
+--- Makefile-gcc	(revision 3206)
++++ Makefile-gcc	(working copy)
+@@ -12,6 +12,7 @@
+ 		pub/libvex_guest_s390x.h		\
+ 		pub/libvex_s390x_common.h		\
+ 		pub/libvex_guest_mips32.h		\
++		pub/libvex_guest_tilegx.h		\
+ 		pub/libvex_guest_offsets.h
+
+ PRIV_HEADERS = 	priv/host_x86_defs.h			\
+@@ -20,6 +21,7 @@
+ 		priv/host_ppc_defs.h			\
+ 		priv/host_s390_defs.h			\
+ 		priv/host_mips_defs.h			\
++		priv/host_tilegx_defs.h			\
+ 		priv/host_generic_maddf.h	        \
+ 		priv/host_generic_regs.h	        \
+ 		priv/host_generic_simd64.h	        \
+@@ -34,8 +36,10 @@
+ 		priv/guest_arm_defs.h			\
+ 		priv/guest_ppc_defs.h			\
+ 		priv/guest_mips_defs.h			\
++		priv/guest_tilegx_defs.h		\
+ 		priv/s390_disasm.h		        \
+ 		priv/s390_defs.h		        \
++		priv/tilegx_disasm.h			\
+ 		priv/ir_match.h			        \
+ 		priv/ir_opt.h
+
+@@ -43,10 +47,11 @@
+ 		priv/ir_match.o			        \
+ 		priv/ir_opt.o				\
+ 		priv/ir_inject.o			\
+-		priv/main_main.o			\
++		priv/multiarch_main_main.o		\
+ 		priv/main_globals.o			\
+ 		priv/main_util.o			\
+ 		priv/s390_disasm.o			\
++		priv/tilegx_disasm.o			\
+ 		priv/host_x86_defs.o			\
+ 		priv/host_amd64_defs.o			\
+ 		priv/host_arm_defs.o			\
+@@ -54,6 +59,7 @@
+ 		priv/host_ppc_defs.o			\
+ 		priv/host_s390_defs.o			\
+ 		priv/host_mips_defs.o			\
++		priv/host_tilegx_defs.o			\
+ 		priv/host_x86_isel.o			\
+ 		priv/host_amd64_isel.o			\
+ 		priv/host_arm_isel.o			\
+@@ -61,6 +67,7 @@
+ 		priv/host_ppc_isel.o			\
+ 		priv/host_s390_isel.o			\
+ 		priv/host_mips_isel.o			\
++		priv/host_tilegx_isel.o			\
+ 		priv/host_generic_maddf.o	        \
+ 		priv/host_generic_regs.o	        \
+ 		priv/host_generic_simd64.o	        \
+@@ -76,6 +83,7 @@
+ 		priv/guest_ppc_helpers.o		\
+ 		priv/guest_s390_helpers.o		\
+ 		priv/guest_mips_helpers.o		\
++		priv/guest_tilegx_helpers.o		\
+ 		priv/guest_x86_toIR.o			\
+ 		priv/guest_amd64_toIR.o			\
+ 		priv/guest_arm_toIR.o			\
+@@ -82,7 +90,8 @@
+ 		priv/guest_arm64_toIR.o			\
+ 		priv/guest_ppc_toIR.o                   \
+ 		priv/guest_s390_toIR.o			\
+-		priv/guest_mips_toIR.o
++		priv/guest_mips_toIR.o			\
++		priv/guest_tilegx_toIR.o
+
+ PUB_INCLUDES = -Ipub
+
+@@ -119,10 +128,6 @@
+ # (the above are for icc 8.0 -- 8.0.0.55 I think)
+ # 186: pointless comparison of unsigned integer with zero
+
+-# kludge: stops V biarch builds screwing up at -j 2 or above
+-# The Right fix is to autoconf/automake-ise vex.
+-.NOTPARALLEL:
+-
+ all: vex
+
+ # Empty, needed for Valgrind
+@@ -254,6 +259,10 @@
+ 	$(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/ir_opt.o \
+ 					 -c priv/ir_opt.c
+
++priv/multiarch_main_main.o: $(ALL_HEADERS) priv/multiarch_main_main.c
++	$(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/multiarch_main_main.o \
++					 -c priv/multiarch_main_main.c
++
+ priv/main_main.o: $(ALL_HEADERS) priv/main_main.c
+ 	$(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/main_main.o \
+ 					 -c priv/main_main.c
+@@ -294,6 +303,10 @@
+ 	$(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/host_mips_defs.o \
+ 					 -c priv/host_mips_defs.c
+
++priv/host_tilegx_defs.o: $(ALL_HEADERS) priv/host_tilegx_defs.c
++	$(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/host_tilegx_defs.o \
++					 -c priv/host_tilegx_defs.c
++
+ priv/host_x86_isel.o: $(ALL_HEADERS) priv/host_x86_isel.c
+ 	$(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/host_x86_isel.o \
+ 					 -c priv/host_x86_isel.c
+@@ -322,6 +335,10 @@
+ 	$(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/host_mips_isel.o \
+ 					 -c priv/host_mips_isel.c
+
++priv/host_tilegx_isel.o: $(ALL_HEADERS) priv/host_tilegx_isel.c
++	$(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/host_tilegx_isel.o \
++					 -c priv/host_tilegx_isel.c
++
+ priv/host_generic_maddf.o: $(ALL_HEADERS) priv/host_generic_maddf.c
+ 	$(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/host_generic_maddf.o \
+ 					 -c priv/host_generic_maddf.c
+@@ -413,3 +430,15 @@
+ priv/guest_mips_toIR.o: $(ALL_HEADERS) priv/guest_mips_toIR.c
+ 	$(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/guest_mips_toIR.o \
+ 					 -c priv/guest_mips_toIR.c
++
++priv/tilegx_disasm.o: $(ALL_HEADERS) priv/tilegx_disasm.c
++	$(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/tilegx_disasm.o \
++					 -c priv/tilegx_disasm.c
++
++priv/guest_tilegx_helpers.o: $(ALL_HEADERS) priv/guest_tilegx_helpers.c
++	$(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/guest_tilegx_helpers.o \
++					 -c priv/guest_tilegx_helpers.c
++
++priv/guest_tilegx_toIR.o: $(ALL_HEADERS) priv/guest_tilegx_toIR.c
++	$(CC) $(CCFLAGS) $(ALL_INCLUDES) -o priv/guest_tilegx_toIR.o \
++					 -c priv/guest_tilegx_toIR.c