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aladdin: Add support for ARM ACP.
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Most of the work is implemented as part of Aladdin; this commit just
connects up the ports.

Change-Id: I8e93c9911b531699933a3c53b8d113ef8b42dff8
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xyzsam committed Sep 29, 2017
1 parent 850f7da commit d459885
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Showing 4 changed files with 13 additions and 7 deletions.
1 change: 1 addition & 0 deletions configs/aladdin/aladdin_se.py
Original file line number Diff line number Diff line change
Expand Up @@ -237,6 +237,7 @@ def get_processes(options):
datapath.ignoreCacheFlush = config.getboolean(accel, "ignore_cache_flush")
datapath.invalidateOnDmaStore = config.getboolean(accel, "invalidate_on_dma_store")
datapath.recordMemoryTrace = config.getboolean(accel, "record_memory_trace")
datapath.enableAcp = config.getboolean(accel, "enable_acp")
if memory_type == "cache":
datapath.cacheSize = config.get(accel, "cache_size")
datapath.cacheBandwidth = config.get(accel, "cache_bandwidth")
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1 change: 1 addition & 0 deletions configs/aladdin/aladdin_template.cfg
Original file line number Diff line number Diff line change
Expand Up @@ -51,6 +51,7 @@ cache_queue_size = 32 ; Max number of cache requests in flight.
cache_bandwidth = 4 ; Number of r/w cache ports.
cache_hit_latency = 1 ; In cycles.
cache_size = 32kB
enable_acp = False ; Connect the ACP port (to L2).


# ================= RARELY USED OPTIONS ===================
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16 changes: 10 additions & 6 deletions configs/common/CacheConfig.py
Original file line number Diff line number Diff line change
Expand Up @@ -206,12 +206,16 @@ def config_cache(options, system):
data_latency=datapath.cacheHitLatency,
tag_latency=datapath.cacheHitLatency,
response_latency=datapath.cacheHitLatency)
if options.l2cache:
datapath.addPrivateL1Dcache(system, system.tol2bus)
datapath.connectPrivateScratchpad(system, system.membus)
else:
datapath.addPrivateL1Dcache(system, system.membus)
datapath.connectPrivateScratchpad(system, system.membus)
# The ability for the accelerator to have an L2 cache has been removed
# for now. The original implementation of attaching the accelerator's
# dcache to the CPU's L2 cache is probably not what users would expect
# anyways.
datapath.addPrivateL1Dcache(system, system.membus)
datapath.connectPrivateScratchpad(system, system.membus)

if datapath.enableAcp:
assert(options.l2cache and "ACP requires an L2 cache!")
datapath.connectAcpPort(system.tol2bus)
return system

# ExternalSlave provides a "port", but when that port connects to a cache,
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2 changes: 1 addition & 1 deletion src/aladdin

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