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A General-purpose Task-parallel Programming System using Modern C++

C++ 10,501 1,228 Updated Jan 14, 2025

Abseil Common Libraries (C++)

C++ 15,356 2,682 Updated Jan 24, 2025

A list of papers, docs, codes about model quantization. This repo is aimed to provide the info for model quantization research, we are continuously improving the project. Welcome to PR the works (p…

1,971 212 Updated Nov 1, 2024

This is originally a collection of papers on neural network accelerators. Now it's more like my selection of research on deep learning and computer architecture.

1,896 383 Updated Jan 6, 2025

[CVPR 2020] This project is the PyTorch implementation of our accepted CVPR 2020 paper : forward and backward information retention for accurate binary neural networks.

Python 179 38 Updated Mar 14, 2020

Pytorch implementation of our paper accepted by NeurIPS 2020 -- Rotated Binary Neural Network

Python 81 20 Updated Dec 30, 2022

Binarized Neural Network (BNN) for pytorch

Python 509 127 Updated Nov 6, 2023

Awesome machine learning for combinatorial optimization papers.

Python 1,776 203 Updated Sep 5, 2024
Python 2 1 Updated Jan 24, 2021

dabnn is an accelerated binary neural networks inference framework for mobile platform

C++ 777 102 Updated Nov 12, 2019

A simple Graph Net in PyTorch

Python 24 13 Updated May 23, 2020

🚆 Fine-grained analysis and visualization of Hangzhou Metro for efficient traveling in metro system. Project report, slide and presentation video included.

C++ 22 1 Updated May 3, 2020

Fast Programmable Nexus Network

C++ 312 87 Updated Oct 28, 2022

Release of stream-specialization software/hardware stack.

Python 120 24 Updated May 5, 2023

This is a repo which contains some details about how to use OpenCL backend (Xilinx/Intel).

C++ 24 Updated Oct 18, 2019

Datasets, Transforms and Models specific to Computer Vision

Python 16,485 6,991 Updated Jan 27, 2025

在FPGA上面实现一个NPU计算单元。能够执行矩阵运算(ADD/ADDi/ADDs/MULT/MULTi/DOT等)、图像处理运算(CONV/POOL等)、非线性映射(RELU/TANH/SIGM等)。

Verilog 212 43 Updated Aug 16, 2018

MAESTRO binary release

Python 22 4 Updated Nov 14, 2019
Verilog 4 5 Updated Aug 7, 2017

Xilinx Tcl Store

Tcl 350 190 Updated Dec 24, 2024

End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.

C++ 227 59 Updated Oct 6, 2022

Python-based Hardware Design Processing Toolkit for Verilog HDL

Python 669 188 Updated Jun 15, 2024

Modified gem5 with new, machine learning based cache management policy

C++ 8 2 Updated Apr 26, 2014

RTL, Cmodel, and testbench for NVDLA

Verilog 1,793 575 Updated Mar 2, 2022

GPGPU microprocessor architecture

C 2,034 356 Updated Nov 8, 2024