Merge branch '2017.3_video_ea'

Merged with the HEAD of the upstream branch that the 2017.4 reVISION platforms
used. This was chosen for the merge because it should be compatible with 2017.4
petalinux projects, SDSoC platforms, and reVISION platforms. The Xilinx doc
suggests the use of the 2017.4 petalinux tag instead, but that will be missing
some code specific for reVISION support.

Documentation/devicetree/bindings/clock/silabs,si5324.txt

@@ -0,0 +1,61 @@
+Binding for Silicon Labs Si5324 programmable i2c clock generator.
+
+Reference
+[1] Si5324 Data Sheet
+    http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5324.pdf
+
+The Si5324 is programmable i2c low-bandwidth, jitter-attenuating, precision
+clock multiplier with up to 2 output clocks. The internal structure of the 
+clock multiplier can be found in [1].
+
+==I2C device node==
+
+Required properties:
+- compatible: shall be "silabs,si5324".
+- reg: i2c device address, shall be 0x68.
+- #clock-cells: from common clock binding; shall be set to 1.
+- clocks: from common clock binding; list of parent clock
+  handles, shall be xtal reference clock or xtal. Corresponding clock
+  input names is "xtal"
+- #address-cells: shall be set to 1.
+- #size-cells: shall be set to 0.
+
+==Child nodes==
+
+Each of the clock outputs can be overwritten individually by
+using a child node to the I2C device node. If a child node for a clock
+output is not set, the eeprom configuration is not overwritten.
+
+Required child node properties:
+- reg: number of clock output.
+- clock-frequency: default output frequency at power on
+
+==Example==
+
+	/* 114.285MHz reference crystal */
+	refhdmi: refhdmi {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <114285000>;
+	};
+
+	/* Si5324 i2c clock generator */
+	si5324: clock-generator@68 {
+		status = "okay";
+		compatible = "silabs,si5324";
+		reg = <0x68>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		#clock-cells = <1>;
+
+		/* input clock(s); the XTAL is hard-wired on the ZCU102 board */
+		clocks = <&refhdmi>;
+		clock-names = "xtal";
+
+		/* output clocks */
+		clk0 {
+			reg = <0>;
+			/* Reference clock output frequency */
+			clock-frequency = <27000000>;
+		};
+	};

Documentation/devicetree/bindings/crypto/zynqmp-rsa.txt

@@ -0,0 +1,12 @@
+Xilinx ZynqMP RSA hw acceleration support
+
+The zynqmp PS-RSA hw accelerator is used to encrypt/decrypt
+the given user data.
+
+Required properties:
+- compatible:	should contain "xlnx,zynqmp-rsa"
+
+Example:
+	xlnx_rsa: zynqmp_rsa {
+		compatible = "xlnx,zynqmp-rsa";
+	};

Documentation/devicetree/bindings/crypto/zynqmp-sha.txt

@@ -0,0 +1,12 @@
+Xilinx ZynqMP SHA3(keccak-384) hw acceleration support.
+
+The ZynqMp PS-SHA hw accelerator is used to calculate the
+SHA3(keccak-384) hash value on the given user data.
+
+Required properties:
+- compatible:	should contain "xlnx,zynqmp-keccak-384"
+
+Example:
+	xlnx_keccak_384: sha384 {
+		compatible = "xlnx,zynqmp-keccak-384";
+	};

Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt

@@ -0,0 +1,67 @@
+* Xilinx PS PCIe Root DMA
+
+Required properties:
+- compatible: Should be "xlnx,ps_pcie_dma-1.00.a"
+- reg: Register offset for Root DMA channels
+- reg-names: Name for the register. Should be "ps_pcie_regbase"
+- interrupts: Interrupt pin for Root DMA
+- interrupt-names: Name for the interrupt. Should be "ps_pcie_rootdma_intr"
+- interrupt-parent: Should be gic in case of zynqmp
+- rootdma: Indicates this platform device is root dma.
+	This is required as the same platform driver will be invoked by pcie end points too
+- dma_vendorid: 16 bit PCIe device vendor id.
+	This can be later used by dma client for matching while using dma_request_channel
+- dma_deviceid: 16 bit PCIe device id
+	This can be later used by dma client for matching while using dma_request_channel
+- numchannels: Indicates number of channels to be enabled for the device.
+	Valid values are from 1 to 4 for zynqmp
+- ps_pcie_channel : One for each channel to be enabled.
+	This array contains channel specific properties.
+	Index 0: Direction of channel
+		Direction of channel can be either PCIe Memory to AXI memory i.e., Host to Card or
+		AXI Memory to PCIe memory i.e., Card to Host
+		PCIe to AXI Channel Direction is represented as 0x1
+		AXI to PCIe Channel Direction is represented as 0x0
+	Index 1: Number of Buffer Descriptors
+		This number describes number of buffer descriptors to be allocated for a channel
+	Index 2: Number of Queues
+		Each Channel has four DMA Buffer Descriptor Queues.
+		By default All four Queues will be managed by Root DMA driver.
+		User may choose to have only two queues either Source and it's Status Queue or
+			Destination and it's Status Queue to be handled by Driver.
+		The other two queues need to be handled by user logic which will not be part of this driver.
+		All Queues on Host is represented by 0x4
+		Two Queues on Host is represented by 0x2
+	Index 3: Coalesce Count
+		This number indicates the number of transfers after which interrupt needs to
+		be raised for the particular channel. The allowed range is from 0 to 255
+	Index 4: Coalesce Count Timer frequency
+		This property is used to control the frequency of poll timer. Poll timer is
+		created for a channel whenever coalesce count value (>= 1) is programmed for the particular
+		channel. This timer is helpful in draining out completed transactions even though interrupt is
+		not generated.
+
+Client Usage:
+	DMA clients can request for these channels using dma_request_channel API
+
+
+Xilinx PS PCIe Root DMA node Example
+++++++++++++++++++++++++++++++++++++
+
+	pci_rootdma: rootdma@fd0f0000 {
+		compatible = "xlnx,ps_pcie_dma-1.00.a";
+		reg = <0x0 0xfd0f0000 0x0 0x1000>;
+		reg-names = "ps_pcie_regbase";
+		interrupts = <0 117 4>;
+		interrupt-names = "ps_pcie_rootdma_intr";
+		interrupt-parent = <&gic>;
+		rootdma;
+		dma_vendorid = /bits/ 16 <0x10EE>;
+		dma_deviceid = /bits/ 16 <0xD021>;
+		numchannels = <0x4>;
+		#size-cells = <0x5>;
+		ps_pcie_channel0 = <0x1 0x7CF 0x4 0x0 0x3E8>;
+		ps_pcie_channel1 = <0x0 0x7CF 0x4 0x0 0x3E8>;
+		ps_pcie_channel2 = <0x1 0x7CF 0x4 0x0 0x3E8>;
+		ps_pcie_channel3 = <0x0 0x7CF 0x4 0x0 0x3E8>;
+    };

Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt

@@ -66,8 +66,6 @@ Optional child node properties:
 Optional child node properties for VDMA:
 - xlnx,genlock-mode: Tells Genlock synchronization is
 	enabled/disabled in hardware.
-- xlnx,fstore-enable: boolean; if defined, it indicates that controller
-	supports frame store configuration.
 Optional child node properties for AXI DMA:
 -dma-channels: Number of dma channels in child node.
 

Documentation/devicetree/bindings/dma/xilinx/xilinx_frmbuf.txt

@@ -0,0 +1,89 @@
+The Xilinx framebuffer DMA engine supports two soft IP blocks: one IP
+block is used for reading video frame data from memory (FB Read) to the device
+and the other IP block is used for writing video frame data from the device
+to memory (FB Write).  Both the FB Read/Write IP blocks are aware of the
+format of the data being written to or read from memory including RGB and
+YUV in packed, planar, and semi-planar formats.  Because the FB Read/Write
+is format aware, only one buffer pointer is needed by the IP blocks even
+when planar or semi-planar format are used.
+
+FB Read Required propertie(s):
+- compatible		: Should be "xlnx,axi-frmbuf-rd-v2"
+
+Note: Compatible string "xlnx,axi-frmbuf-rd" and the hardware it
+represented is no longer supported.
+
+FB Write Required propertie(s):
+- compatible		: Should be "xlnx,axi-frmbuf-wr-v2"
+
+Note: Compatible string "xlnx,axi-frmbuf-wr" and the hardware it
+represented is no longer supported.
+
+Required Properties Common to both FB Read and FB Write:
+- #dma-cells		: should be 1
+- interrupt-parent	: Interrupt controller the interrupt is routed through
+- interrupts		: Should contain DMA channel interrupt
+- reset-gpios		: Should contain GPIO reset phandle
+- reg			: Memory map for module access
+- xlnx,dma-addr-width	: Size of dma address pointer in IP (either 32 or 64)
+- xlnx,vid-formats	: A list of strings indicating what video memory
+			  formats the IP has been configured to support.
+			  See VIDEO FORMATS table below and examples.
+
+VIDEO FORMATS
+The following table describes the legal string values to be used for
+the xlnx,vid-formats property.  To the left is the string value and the
+two columns to the right describe how this is mapped to an equivalent V4L2
+and DRM fourcc code---respectively---by the driver.
+
+IP FORMAT	DTS String	V4L2 Fourcc		DRM Fourcc
+-------------|----------------|----------------------|---------------------
+RGB8		bgr888		V4L2_PIX_FMT_RGB24	DRM_FORMAT_BGR888
+RGBX8		xbgr8888	V4L2_PIX_FMT_BGRX32	DRM_FORMAT_XBGR8888
+RGBA8		<none>		<not supported>		<not supported>
+BGRA8		<none>		<not supported>		<not supported>
+BGRX8		xrgb8888	V4L2_PIX_FMT_XRGB32	DRM_FORMAT_XRGB8888
+RGBX10		xbgr2101010	V4L2_PIX_FMT_XBGR30	DRM_FORMAT_XBGR2101010
+YUV8		vuy888		V4L2_PIX_FMT_VUY24	DRM_FORMAT_VUY888
+YUVX8		xvuy8888	V4L2_PIX_FMT_XVUY32	DRM_FORMAT_XVUY8888
+YUYV8		yuyv		V4L2_PIX_FMT_YUYV	DRM_FORMAT_YUYV
+UYVY8		uyvy		V4L2_PIX_FMT_UYVY	DRM_FORMAT_UYVY
+YUVA8		<none>		<not supported>		<not supported>
+YUVX10		yuvx2101010	V4L2_PIX_FMT_XVUY10	DRM_FORMAT_XVUY2101010
+Y8		y8		V4L2_PIX_FMT_GREY	DRM_FORMAT_Y8
+Y10		y10		V4L2_PIX_FMT_Y10	DRM_FORMAT_Y10
+Y_UV8		nv16		V4L2_PIX_FMT_NV16	DRM_FORMAT_NV16
+Y_UV8		nv16		V4L2_PIX_FMT_NV16M	DRM_FORMAT_NV16
+Y_UV8_420	nv12		V4L2_PIX_FMT_NV12	DRM_FORMAT_NV12
+Y_UV8_420	nv12		V4L2_PIX_FMT_NV12M	DRM_FORMAT_NV12
+Y_UV10		xv20		V4L2_PIX_FMT_XV20M	DRM_FORMAT_XV20
+Y_UV10_420	xv15		V4L2_PIX_FMT_XV15M	DRM_FORMAT_XV15
+
+
+Examples
+
+FB Read Example:
+++++++++
+v_frmbuf_rd_0: v_frmbuf_rd@80000000 {
+	#dma-cells = <1>;
+	compatible = "xlnx,axi-frmbuf-rd-v2";
+	interrupt-parent = <&gic>;
+	interrupts = <0 92 4>;
+	reset-gpios = <&gpio 80 1>;
+	reg = <0x0 0x80000000 0x0 0x10000>;
+	xlnx,dma-addr-width = <32>;
+	xlnx,vid-formats = "bgr888","xbgr8888";
+};
+
+FB Write Example:
+++++++++
+v_frmbuf_wr_0: v_frmbuf_wr@80000000 {
+	#dma-cells = <1>;
+	compatible = "xlnx,axi-frmbuf-wr-v2";
+	interrupt-parent = <&gic>;
+	interrupts = <0 92 4>;
+	reset-gpios = <&gpio 80 1>;
+	reg = <0x0 0x80000000 0x0 0x10000>;
+	xlnx,dma-addr-width = <64>;
+	xlnx,vid-formats = "bgr888","yuyv","nv16","nv12";
+};

Documentation/devicetree/bindings/drm/xilinx/dsi.txt

@@ -5,8 +5,6 @@ The IP core supports transmission of video data in MIPI DSI protocol.
 Required properties:
  - compatible: Should be "xlnx,mipi-dsi-tx-subsystem".
  - reg: Base address and size of the IP core.
- - xlnx,dsi-pixels-perbeat: Number of pixels per beat. The value should
-   be one of 1, 2, or 4.
  - xlnx,dsi-datatype: Color format. The value should be one of "MIPI_DSI_FMT_RGB888",
    "MIPI_DSI_FMT_RGB666", "MIPI_DSI_FMT_RGB666_PACKED" or "MIPI_DSI_FMT_RGB565".
  - simple_panel: The subnode for connected panel. This represents the
@@ -43,7 +41,6 @@ Example:
 		compatible = "xlnx,mipi-dsi-tx-subsystem";
 		reg = <0x0 0x80000000 0x0 0x10000>;
 		xlnx,dsi-num-lanes = <4>;
-		xlnx,dsi-pixels-perbeat = <1>;
 		xlnx,dsi-data-type = <MIPI_DSI_FMT_RGB888>;
 		#address-cells = <1>;
 		#size-cells = <0>;

Documentation/devicetree/bindings/drm/xilinx/sdi.txt

@@ -0,0 +1,34 @@
+Device-Tree bindings for Xilinx SDI Tx IP core
+
+The IP core supports transmission of video data in SDI Tx: protocol.
+
+Required properties:
+ - compatible: Should be "xlnx,v-smpte-uhdsdi-tx-ss".
+ - interrupts: Interrupt number.
+ - interrupts-parent: phandle for interrupt controller.
+ - reg: Base address and size of the IP core.
+ - ports: Connects to the drm device node through device graph binding.
+   The port should contain a 'remote-endpoint' subnode that points to the
+   endpoint in the port of the drm device node. Refer to
+   Documentation/devicetree/bindings/graph.txt.
+ - xlnx,vtc: vtc phandle
+
+Example:
+
+		v_smpte_uhdsdi_tx_ss: v_smpte_uhdsdi_tx_ss@80020000 {
+			compatible = "xlnx,v-smpte-uhdsdi-tx-ss";
+			interrupt-parent = <&gic>;
+			interrupts = <0 90 4>;
+			reg = <0x0 0x80020000 0x0 0x10000>;
+			xlnx,vtc = <&v_tc_0>;
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				port@0 {
+					reg = <0>;
+					sdi_port: endpoint {
+						remote-endpoint = <&drm_port>;
+					};
+				};
+		        };
+		};

Documentation/devicetree/bindings/drm/xilinx/xilinx_drm.txt

@@ -58,8 +58,7 @@ Required planes properties:
 
 Required plane properties:
  - dmas: the phandle list of DMA specifiers
- - dma-names: the indentifier strings for DMAs. The value should be "dma"
-   followed by the index: "dma0", "dma1".
+ - dma-names: the identifier strings for DMAs.
  - xlnx,rgb2yuv: the phandle for rgb2ycrcb IP if used for plane
  - xlnx,cresample: the phandle for chroma resampler IP if used for plane
 
@@ -78,7 +77,7 @@ vdma - [remap] - rgb2yuv - cresample - [axi2vid] - adv7511
 			xlnx,pixel-format = "yuv422";
 			plane0 {
 				dma = <&axi_vdma_0>;
-				dma-names = "dma0";
+				dma-names = "axi_vdma_0";
 				xlnx,rgb2yuv = <&v_rgb2ycrcb_0>;
 				xlnx,cresample = <&v_cresample_0>;
 			};
@@ -102,11 +101,11 @@ vdma - [remap] - rgb2yuv -|                               |
 			xlnx,pixel-format = "yuv422";
 			plane0 {
 				dma = <&axi_vdma_0>;
-				dma-names = "dma0";
+				dma-names = "axi_vdma_0";
 			};
 			plane1 {
 				dma = <&axi_vdma_1>;
-				dma-names = "dma0";
+				dma-names = "axi_vdma_1";
 				xlnx,rgb2yuv = <&v_rgb2ycrcb_0>;
 			};
 		};
@@ -125,13 +124,15 @@ dpdma - ZynqMP DP subsystem - DP
 			xlnx,pixel-format = "rgb565";
 			plane0 {
 				dmas = <&xlnx_dpdma 3>;
-				dma-names = "dma0";
+				dma-names = "xlnx_dpdma";
 			};
 			plane1 {
 				dmas = <&xlnx_dpdma 0>,
 				       <&xlnx_dpdma 1>,
 				       <&xlnx_dpdma 2>;
-				dma-names = "dma0", "dma1", "dma2";
+				dma-names = "xlnx_dpdma_0",
+				            "xlnx_dpdma_1",
+				            "xlnx_dpdma_2";
 			};
 		};
 	};
@@ -154,7 +155,7 @@ vdma - Xilinx MIPI DSI
 			xlnx,pixel-format = "rgb888";
 			plane0 {
 				dmas = <&axi_vdma_0 0>;
-				dma-names = "dma0";
+				dma-names = "axi_vdma_0";
 			};
 		};
 	};