mb/hp: Add new port for compaq_8300_elite_usdt

New port based on autoport.

Autoport worked with minor tweaks, but fan speeds went almost
immediately to the maximum. They are controlled by the NPCD379
Super I/O which isn't supported by coreboot.

But coreboot already has code for NPCD378,
which HP Compaq 8200 SFF makes use of.

So SuperIO configuration was copied from the 8200 SFF port.
It seems to work without any issues in "normal" use.
Most importantly, fan speed control seems to work correctly.

However this means that some of the SuperIO LDNs may be configured
incorrectly. See the comments on Gerrit for more information.

The following is tested and is working:
* Native raminit with both DIMMs
* Libgfxinit textmode and framebuffer on both DisplayPorts and VGA
* External USB2 and USB3 ports: they all work
* USB 3.0 SuperSpeed on Linux-libre (rear, 4 ports)
* Ethernet
* Mini-PCIe WLAN
* SATA: 2.5" SSD and optical drive bay
* Booting Live Linuxes from DVD and USB with SeaBIOS 1.16.1
* GRUB (with Libreboot config)
* PS/2 keyboard and mouse
* S3 suspend and resume, wake using USB keyboard
* Headphone output, line out, internal speaker
* Wake on LAN
* Rebooting
* CMOS options & nvramcui

Untested:
* mSATA slot. The SATA port needs to be enabled on devicetree
  too, but I'm unable to test due to lack of hardware
* Line in, mic input
* MXM graphics card
* EHCI debug

Not working:
* Mini-PCIe USB: I couldn't get it working on vendor BIOS either, so
  maybe it just isn't present
* PS/2 keyboard wake from S3

Change-Id: I2dc31778c2aa1987d5acdf355973a203dd0bb3a3
Signed-off-by: Riku Viitanen <[email protected]>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74906
Reviewed-by: Kyösti Mälkki <[email protected]>
Tested-by: build bot (Jenkins) <[email protected]>

Documentation/mainboard/hp/compaq_8300_usdt.md

@@ -0,0 +1,66 @@
+# HP Compaq 8300 Elite USDT
+
+This page describes how to run coreboot on the [Compaq 8300 Elite USDT] desktop
+from [HP].
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+-------------+
+| Type                | Value       |
++=====================+=============+
+| Socketed flash      | no          |
++---------------------+-------------+
+| Model               | W25Q128BVFG |
++---------------------+-------------+
+| Size                | 16 MiB      |
++---------------------+-------------+
+| In circuit flashing | yes         |
++---------------------+-------------+
+| Package             | SOIC-16     |
++---------------------+-------------+
+| Write protection    | No          |
++---------------------+-------------+
+| Dual BIOS feature   | No          |
++---------------------+-------------+
+```
+
+### Internal programming
+
+TODO: investigate
+
+The board has two jumpers that might be relevant: FDO (Flash Descriptor Override) and BB (?).
+
+### External programming
+
+Remove the lid. The flash chip can be found on the edge opposite to the CPU.
+There is a spot for a "ROM RCVRY" header next to the flash chip but it is
+unpopulated. If you don't feel like using a clip, you can easily solder
+a standard pin header there yourself and use it for programming.
+
+Programming powers some parts of the board. Programming when
+Wake on LAN is active works great.
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
++------------------+--------------------------------------------------+
+| Southbridge      | bd82x6x                                          |
++------------------+--------------------------------------------------+
+| CPU              | model_206ax                                      |
++------------------+--------------------------------------------------+
+| SuperIO          | NPCD379HAKFX                                     |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel ME                                         |
++------------------+--------------------------------------------------+
+```
+
+### SuperIO
+
+This board has a Nuvoton NPCD379 SuperIO chip. Fan speed and PS/2 keyboard work
+fine using coreboot's existing code for :doc:`../../superio/nuvoton/npcd378`.
+
+[Compaq 8300 USDT]: https://support.hp.com/gb-en/product/hp-compaq-elite-8300-ultra-slim-pc/5232866
+[HP]: https://www.hp.com/

src/mainboard/hp/compaq_elite_8300_usdt/Kconfig

@@ -0,0 +1,38 @@
+if BOARD_HP_COMPAQ_ELITE_8300_USDT
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select INTEL_INT15
+	select MAINBOARD_HAS_TPM1
+	select MAINBOARD_HAS_LIBGFXINIT
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select MEMORY_MAPPED_TPM
+	select NORTHBRIDGE_INTEL_SANDYBRIDGE
+	select SERIRQ_CONTINUOUS_MODE
+	select SOUTHBRIDGE_INTEL_C216
+	select SUPERIO_NUVOTON_NPCD378
+	select USE_NATIVE_RAMINIT
+
+config CBFS_SIZE
+	default 0x570000
+
+config MAINBOARD_DIR
+	default "hp/compaq_elite_8300_usdt"
+
+config MAINBOARD_PART_NUMBER
+	default "HP Compaq Elite 8300 USDT"
+
+config VGA_BIOS_ID
+	default "8086,0152"
+
+config DRAM_RESET_GATE_GPIO
+	default 60
+
+config USBDEBUG_HCD_INDEX # FIXME: check this
+	default 2
+endif

src/mainboard/hp/compaq_elite_8300_usdt/Kconfig.name

@@ -0,0 +1,2 @@
+config BOARD_HP_COMPAQ_ELITE_8300_USDT
+	bool "Compaq Elite 8300 USDT"

src/mainboard/hp/compaq_elite_8300_usdt/Makefile.inc

@@ -0,0 +1,5 @@
+bootblock-y += early_init.c
+bootblock-y += gpio.c
+romstage-y += early_init.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads

src/mainboard/hp/compaq_elite_8300_usdt/acpi/ec.asl

@@ -0,0 +1 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */

src/mainboard/hp/compaq_elite_8300_usdt/acpi/platform.asl

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method(_WAK, 1)
+{
+	Return(Package() {0, 0})
+}
+
+Method(_PTS, 1)
+{
+}

src/mainboard/hp/compaq_elite_8300_usdt/acpi/superio.asl

@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Copied over from compaq_8200_elite_sff/acpi/superio.asl */
+
+#include <superio/nuvoton/npcd378/acpi/superio.asl>
+
+Scope (\_GPE)
+{
+	Method (_L0D, 0, NotSerialized)
+	{
+		Notify (\_SB.PCI0.EHC1, 0x02)
+		Notify (\_SB.PCI0.EHC2, 0x02)
+		//FIXME: Add GBE device
+		//Notify (\_SB.PCI0.GBE, 0x02)
+	}
+
+	Method (_L09, 0, NotSerialized)
+	{
+		Notify (\_SB.PCI0.RP01, 0x02)
+		Notify (\_SB.PCI0.RP02, 0x02)
+		Notify (\_SB.PCI0.RP03, 0x02)
+		Notify (\_SB.PCI0.RP04, 0x02)
+		Notify (\_SB.PCI0.RP05, 0x02)
+		Notify (\_SB.PCI0.RP06, 0x02)
+		Notify (\_SB.PCI0.RP07, 0x02)
+		Notify (\_SB.PCI0.RP08, 0x02)
+		Notify (\_SB.PCI0.PEGP, 0x02)
+	}
+}

src/mainboard/hp/compaq_elite_8300_usdt/acpi_tables.c

@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi_gnvs.h>
+#include <soc/nvs.h>
+
+void mainboard_fill_gnvs(struct global_nvs *gnvs)
+{
+	/* Temperature at which OS will shutdown */
+	gnvs->tcrt = 100;
+	/* Temperature at which OS will throttle CPU */
+	gnvs->tpsv = 90;
+}

src/mainboard/hp/compaq_elite_8300_usdt/board_info.txt

@@ -0,0 +1,6 @@
+Category: mini
+ROM protocol: SPI
+ROM socketed: n
+ROM package: SOIC-16
+Flashrom support: y
+Release year: 2012

src/mainboard/hp/compaq_elite_8300_usdt/cmos.default

@@ -0,0 +1,6 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Enable
+nmi=Enable
+sata_mode=AHCI
+gfx_uma_size=32M

src/mainboard/hp/compaq_elite_8300_usdt/cmos.layout

@@ -0,0 +1,73 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0	120	r	0	reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	4	boot_option
+388	4	h	0	reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395	4	e	6	debug_level
+
+# coreboot config options: southbridge
+408	1	e	1	nmi
+409	2	e	7	power_on_after_fail
+
+421	1	e	9	sata_mode
+
+# coreboot config options: northbridge
+432	3	e	11	gfx_uma_size
+
+448	128	r	0	vbnv
+
+# SandyBridge MRC Scrambler Seed values
+896	32	r	0	mrc_scrambler_seed
+928	32	r	0	mrc_scrambler_seed_s3
+960	16	r	0	mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984	16	h	0	check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID	value	text
+1	0	Disable
+1	1	Enable
+2	0	Enable
+2	1	Disable
+4	0	Fallback
+4	1	Normal
+6	0	Emergency
+6	1	Alert
+6	2	Critical
+6	3	Error
+6	4	Warning
+6	5	Notice
+6	6	Info
+6	7	Debug
+6	8	Spew
+7	0	Disable
+7	1	Enable
+7	2	Keep
+9	0	AHCI
+9	1	IDE
+11	0	32M
+11	1	64M
+11	2	96M
+11	3	128M
+11	4	160M
+11	5	192M
+11	6	224M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984