Skip to content

Commit

Permalink
mb/x11-lga1151-series: Add x11ssw-f
Browse files Browse the repository at this point in the history 
This board is similar to x11ssm-f but has a proprietary form factor with
NVMe and a single x16 slot (potentially bifurcated to 2x x8) and a x4
slot.

Change-Id: I53a0b6012ae64cf1ba4b625f11aaf771637307f3
Signed-off-by: Kieran Kunhya <[email protected]>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77610
Tested-by: build bot (Jenkins) <[email protected]>
Reviewed-by: Michael Niewöhner <[email protected]>
  • Loading branch information
@kierank @c0d3z3r0
kierank authored and c0d3z3r0 committed Sep 21, 2023
1 parent 44bbf6c commit c0ef33f
Show file tree
Hide file tree
Showing 8 changed files with 470 additions and 0 deletions.
1 change: 1 addition & 0 deletions Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,7 @@ Controller etc.
- [X11SSH-TF](x11ssh-tf/x11ssh-tf.md)
- [X11SSH-F/LN4F](x11ssh-f/x11ssh-f.md)
- [X11SSM-F](x11ssm-f/x11ssm-f.md)
- [X11SSW-F](x11ssw-f/x11ssw-f.md)

## Required proprietary blobs

Expand Down
76 changes: 76 additions & 0 deletions Documentation/mainboard/supermicro/x11-lga1151-series/x11ssw-f/x11ssw-f.md
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,76 @@
# Supermicro X11SSW-F

This section details how to run coreboot on the [Supermicro X11SSW-F].

## Flashing coreboot

Flashing was performed through the BMC web interface, when a valid license was entered.

## Tested and working

- SeaBIOS version 1.16.2 Payload loading Ubuntu 22.04, kernel 5.4.0-162-generic
- ECC ram (Linux' ie31200 driver works)
- USB ports
- Ethernet
- SATA ports
- RS232 external
- Left PCIe slot
- BMC (IPMI)
- VGA on Aspeed

## Untested
- Right PCIe slot
- NVMe
- TPM on TPM expansion header

## Known issues

- See general issue section
- LNXTHERM missing
- S3 resume not working

## Technology

```eval_rst
+------------------+--------------------------------------------------+
| CPU | Intel Kaby Lake |
+------------------+--------------------------------------------------+
| PCH | Intel C236 |
+------------------+--------------------------------------------------+
| Coprocessor | Intel SPS (server version of the ME) |
+------------------+--------------------------------------------------+
| Super I/O | ASPEED AST2400 |
+------------------+--------------------------------------------------+
| Ethernet | 2x Intel I210-AT 1 GbE |
| | 1x dedicated BMC |
+------------------+--------------------------------------------------+
| PCIe slots | 1x 3.0 x16 (Left Riser) |
| | 1x 3.0 x4 (Right Riser in x16) |
| | 1x 3.0 x4 (NVMe) |
+------------------+--------------------------------------------------+
| USB slots | 2x USB 2.0 (ext) |
| | 2x USB 3.0 (ext) |
| | 1x USB 3.0 (int) |
| | 1x dual USB 3.0 header |
| | 2x dual USB 2.0 header |
+------------------+--------------------------------------------------+
| SATA slots | 6x S-ATA III |
+------------------+--------------------------------------------------+
| Other slots | 1x RS232 (ext) |
| | 1x RS232 header |
| | 1x TPM header |
| | 1x Power SMB header |
| | 6x PWM Fan connector |
| | 1x Chassis Intrusion Header |
+------------------+--------------------------------------------------+
```

## Extra links

- [Supermicro X11SSW-F]
- [Board manual]

[Supermicro X11SSW-F]: https://www.supermicro.com/en/products/motherboard/x11ssw-f
[Board manual]: https://www.supermicro.com/manuals/motherboard/C236/MNL-1784.pdf
[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376
[IPMI]: ../../../../drivers/ipmi_kcs.md
3 changes: 3 additions & 0 deletions src/mainboard/supermicro/x11-lga1151-series/Kconfig
View file
Original file line number Diff line number Diff line change
Expand Up @@ -29,6 +29,7 @@ config MAINBOARD_PART_NUMBER
default "X11SSH-TF" if BOARD_SUPERMICRO_X11SSH_TF
default "X11SSM-F" if BOARD_SUPERMICRO_X11SSM_F
default "X11SSH-F/LN4F" if BOARD_SUPERMICRO_X11SSH_F
default "X11SSW-F" if BOARD_SUPERMICRO_X11SSW_F

config MAINBOARD_DIR
default "supermicro/x11-lga1151-series"
Expand All @@ -37,6 +38,7 @@ config VARIANT_DIR
default "x11ssh-tf" if BOARD_SUPERMICRO_X11SSH_TF
default "x11ssm-f" if BOARD_SUPERMICRO_X11SSM_F
default "x11ssh-f" if BOARD_SUPERMICRO_X11SSH_F
default "x11ssw-f" if BOARD_SUPERMICRO_X11SSW_F

config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
Expand Down Expand Up @@ -85,5 +87,6 @@ config SUPERMICRO_BOARDID
default "0896" if BOARD_SUPERMICRO_X11SSM_F
default "089C" if BOARD_SUPERMICRO_X11SSH_TF
default "0884" if BOARD_SUPERMICRO_X11SSH_F
default "089B" if BOARD_SUPERMICRO_X11SSW_F

endif # BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES
4 changes: 4 additions & 0 deletions src/mainboard/supermicro/x11-lga1151-series/Kconfig.name
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,3 +9,7 @@ config BOARD_SUPERMICRO_X11SSM_F
config BOARD_SUPERMICRO_X11SSH_F
bool "X11SSH-F/LN4F"
select BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES

config BOARD_SUPERMICRO_X11SSW_F
bool "X11SSW-F"
select BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES
7 changes: 7 additions & 0 deletions src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/board_info.txt
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,7 @@
Category: server
Vendor name: Supermicro
Board name: X11SSW-F
Board URL: https://www.supermicro.com/en/products/motherboard/X11SSW-F
ROM protocol: SPI
ROM socketed: n
Flashrom support: y
230 changes: 230 additions & 0 deletions src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/gpio.c
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,230 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <mainboard/gpio.h>
#include <soc/gpe.h>
#include <soc/gpio.h>

static const struct pad_config gpio_table[] = {
/* GPIO Group GPP_A */
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1),
PAD_NC(GPP_A12, NONE),
PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
PAD_NC(GPP_A17, NONE),
PAD_NC(GPP_A18, NONE),
/* GPP_A19 - RESERVED */
PAD_NC(GPP_A20, NONE),
PAD_NC(GPP_A21, NONE),
PAD_NC(GPP_A22, NONE),
PAD_NC(GPP_A23, NONE),
PAD_CFG_GPO(GPP_B0, 1, DEEP),
PAD_CFG_GPO(GPP_B1, 1, DEEP),
PAD_NC(GPP_B2, NONE),
PAD_NC(GPP_B3, NONE),
PAD_NC(GPP_B4, NONE),
PAD_NC(GPP_B5, NONE),
PAD_NC(GPP_B6, NONE),
PAD_NC(GPP_B7, NONE),
PAD_NC(GPP_B8, NONE),
PAD_NC(GPP_B9, NONE),
PAD_NC(GPP_B10, NONE),
PAD_CFG_GPO(GPP_B11, 0, DEEP),
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1),
PAD_NC(GPP_B15, NONE),
PAD_NC(GPP_B16, NONE),
PAD_NC(GPP_B17, NONE),
PAD_NC(GPP_B18, NONE),
PAD_NC(GPP_B19, NONE),
PAD_CFG_GPO(GPP_B20, 1, PLTRST),
PAD_NC(GPP_B21, NONE),
PAD_NC(GPP_B22, NONE),
PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2),

/* GPIO Group GPP_C */
/* GPP_C0 - RESERVED */
/* GPP_C1 - RESERVED */
PAD_NC(GPP_C2, NONE),
/* GPP_C3 - RESERVED */
/* GPP_C4 - RESERVED */
PAD_CFG_GPO(GPP_C5, 1, DEEP),
/* GPP_C6 - RESERVED */
/* GPP_C7 - RESERVED */
PAD_NC(GPP_C8, NONE),
PAD_NC(GPP_C9, NONE),
PAD_NC(GPP_C10, NONE),
PAD_NC(GPP_C11, NONE),
PAD_NC(GPP_C12, NONE),
PAD_NC(GPP_C13, NONE),
PAD_NC(GPP_C14, NONE),
PAD_NC(GPP_C15, NONE),
PAD_NC(GPP_C16, NONE),
PAD_NC(GPP_C17, NONE),
PAD_NC(GPP_C18, NONE),
PAD_NC(GPP_C19, NONE),
PAD_NC(GPP_C20, NONE),
PAD_NC(GPP_C21, NONE),
PAD_CFG_GPI_SMI(GPP_C22, UP_20K, DEEP, EDGE_SINGLE, NONE),
PAD_NC(GPP_C23, NONE),

/* GPIO Group GPP_D */
PAD_NC(GPP_D0, NONE),
PAD_CFG_GPO(GPP_D1, 1, DEEP),
PAD_CFG_GPI_NMI(GPP_D2, UP_20K, DEEP, EDGE_SINGLE, NONE),
PAD_NC(GPP_D3, NONE),
PAD_CFG_GPO(GPP_D4, 0, PLTRST),
PAD_NC(GPP_D5, NONE),
PAD_NC(GPP_D6, NONE),
PAD_NC(GPP_D7, NONE),
PAD_NC(GPP_D8, NONE),
PAD_NC(GPP_D9, NONE),
PAD_NC(GPP_D10, NONE),
PAD_NC(GPP_D11, NONE),
PAD_NC(GPP_D12, NONE),
PAD_NC(GPP_D13, NONE),
PAD_NC(GPP_D14, NONE),
PAD_NC(GPP_D15, NONE),
PAD_NC(GPP_D16, NONE),
PAD_NC(GPP_D17, NONE),
PAD_CFG_GPO(GPP_D18, 1, PLTRST),
PAD_CFG_GPO(GPP_D19, 1, PLTRST),
PAD_NC(GPP_D20, NONE),
PAD_CFG_GPO(GPP_D21, 0, DEEP),
PAD_NC(GPP_D22, NONE),
PAD_NC(GPP_D23, NONE),

/* GPIO Group GPP_E */
PAD_NC(GPP_E0, NONE),
PAD_NC(GPP_E1, NONE),
PAD_NC(GPP_E2, NONE),
PAD_NC(GPP_E3, NONE),
PAD_NC(GPP_E4, NONE),
PAD_NC(GPP_E5, NONE),
PAD_CFG_GPI_NMI(GPP_E6, UP_20K, PLTRST, EDGE_SINGLE, NONE),
PAD_NC(GPP_E7, NONE),
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),

/* GPIO Group GPP_F */
PAD_NC(GPP_F0, NONE),
PAD_NC(GPP_F1, NONE),
PAD_NC(GPP_F2, NONE),
PAD_NC(GPP_F3, NONE),
PAD_NC(GPP_F4, NONE),
PAD_CFG_GPI_APIC_HIGH(GPP_F5, NONE, PLTRST),
PAD_CFG_GPO(GPP_F6, 1, PLTRST),
PAD_CFG_GPO(GPP_F7, 1, PLTRST),
PAD_CFG_GPO(GPP_F8, 1, PLTRST),
PAD_NC(GPP_F9, NONE),
PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
PAD_NC(GPP_F14, NONE),
PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
PAD_NC(GPP_F17, NONE),
PAD_NC(GPP_F18, NONE),
PAD_NC(GPP_F19, NONE),
PAD_NC(GPP_F20, NONE),
PAD_NC(GPP_F21, NONE),
PAD_NC(GPP_F22, NONE),
PAD_CFG_GPO(GPP_F23, 0, RSMRST),
PAD_NC(GPP_G0, NONE),
PAD_NC(GPP_G1, NONE),
PAD_NC(GPP_G2, NONE),
PAD_NC(GPP_G3, NONE),
PAD_NC(GPP_G4, NONE),
PAD_NC(GPP_G5, NONE),
PAD_NC(GPP_G6, NONE),
PAD_NC(GPP_G7, NONE),
PAD_NC(GPP_G8, NONE),
PAD_NC(GPP_G9, NONE),
PAD_NC(GPP_G10, NONE),
PAD_NC(GPP_G11, NONE),
PAD_NC(GPP_G12, NONE),
PAD_NC(GPP_G13, NONE),
PAD_NC(GPP_G14, NONE),
PAD_NC(GPP_G15, NONE),
PAD_NC(GPP_G16, NONE),
PAD_NC(GPP_G17, NONE),
PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1),
PAD_NC(GPP_G20, NONE),
PAD_NC(GPP_G21, NONE),
PAD_NC(GPP_G22, NONE),
PAD_NC(GPP_G23, NONE),
PAD_CFG_GPO(GPP_H0, 1, DEEP),
PAD_NC(GPP_H1, NONE),
PAD_CFG_GPO(GPP_H2, 1, DEEP),
PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1),
PAD_NC(GPP_H4, NONE),
PAD_CFG_GPO(GPP_H5, 1, PLTRST),
PAD_CFG_GPO(GPP_H6, 1, PLTRST),
PAD_CFG_GPO(GPP_H7, 1, PLTRST),
PAD_CFG_GPO(GPP_H8, 1, PLTRST),
PAD_CFG_GPO(GPP_H9, 1, PLTRST),
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),
PAD_NC(GPP_H12, NONE),
PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1),
PAD_NC(GPP_H15, NONE),
PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
PAD_NC(GPP_H18, NONE),
PAD_CFG_GPO(GPP_H19, 1, PLTRST),
PAD_CFG_GPO(GPP_H20, 1, PLTRST),
PAD_CFG_GPO(GPP_H21, 1, PLTRST),
PAD_CFG_GPO(GPP_H22, 1, PLTRST),
PAD_CFG_GPO(GPP_H23, 1, PLTRST),

/* GPIO Group GPD */
PAD_NC(GPD0, NONE),
PAD_NC(GPD1, NONE),
PAD_CFG_NF(GPD2, NONE, PWROK, NF1),
PAD_CFG_NF(GPD3, NONE, PWROK, NF1),
PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
PAD_NC(GPD7, NONE),
PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
PAD_NC(GPD9, NONE),
PAD_NC(GPD10, NONE),
PAD_NC(GPD11, NONE),

/* GPIO Group GPP_I */
PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1),
PAD_NC(GPP_I4, NONE),
PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1),
};

void mainboard_configure_gpios(void)
{
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
}
22 changes: 22 additions & 0 deletions src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/gpio_early.c
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,22 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <mainboard/gpio.h>
#include <soc/gpio.h>

static const struct pad_config early_gpio_table[] = {
/* Early LPC configuration in romstage */
PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
};

void mainboard_configure_early_gpios(void)
{
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
}
Loading

0 comments on commit c0ef33f

Please sign in to comment.