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SystemRDL 2.0 language compiler front-end

C++ 250 70 Updated Mar 9, 2025

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Verilog 198 71 Updated Oct 21, 2024

UVM SystemC source, with my own additions

C++ 6 1 Updated Aug 8, 2017
SystemVerilog 197 63 Updated Mar 6, 2025