Minor improvements

hypeartist · Feb 19, 2017 · 9ceb071 · 9ceb071
1 parent c8c16f3
commit 9ceb071
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Showing 3 changed files with 7 additions and 10 deletions.
diff --git a/src/asmjit/base/cpuinfo.cpp b/src/asmjit/base/cpuinfo.cpp
@@ -285,10 +285,9 @@ static void ASMJIT_INLINE x86CallCpuId(CpuIdResult* result, uint32_t inEax, uint
         "=c"(result->ecx),
         "=d"(result->edx)
       : "a"(inEax),
-        "c"(inEcx)
-  );
+        "c"(inEcx));
 #elif (ASMJIT_CC_GCC || ASMJIT_CC_CLANG || ASMJIT_CC_INTEL) && ASMJIT_ARCH_X64
-  __asm__ __volatile__( \
+  __asm__ __volatile__(
     "mov %%rbx, %%rdi\n"
     "cpuid\n"
     "xchg %%rdi, %%rbx\n"
@@ -297,8 +296,7 @@ static void ASMJIT_INLINE x86CallCpuId(CpuIdResult* result, uint32_t inEax, uint
         "=c"(result->ecx),
         "=d"(result->edx)
       : "a"(inEax),
-        "c"(inEcx)
-  );
+        "c"(inEcx));
 #else
 # error "[asmjit] x86CallCpuid() - Unsupported compiler."
 #endif

diff --git a/src/asmjit/base/func.h b/src/asmjit/base/func.h
@@ -214,8 +214,9 @@ struct CallConv {
   };
 
   //! Passed registers' order.
-  struct RegOrder {
+  union RegOrder {
     uint8_t id[kNumRegArgsPerKind];      //!< Passed registers, ordered.
+    uint32_t packed[(kNumRegArgsPerKind + 3) / 4];
   };
 
   // --------------------------------------------------------------------------
@@ -304,8 +305,8 @@ struct CallConv {
   ASMJIT_INLINE void _setPassedPacked(uint32_t kind, uint32_t p0, uint32_t p1) noexcept {
     ASMJIT_ASSERT(kind < kMaxVRegKinds);
 
-    reinterpret_cast<uint32_t*>(_passedOrder[kind].id)[0] = p0;
-    reinterpret_cast<uint32_t*>(_passedOrder[kind].id)[1] = p1;
+    _passedOrder[kind].packed[0] = p0;
+    _passedOrder[kind].packed[1] = p1;
   }
 
   ASMJIT_INLINE void setPassedToNone(uint32_t kind) noexcept {

diff --git a/src/asmjit/x86/x86assembler.cpp b/src/asmjit/x86/x86assembler.cpp
@@ -2947,14 +2947,12 @@ Error X86Assembler::_emit(uint32_t instId, const Operand_& o0, const Operand_& o
       ASMJIT_FALLTHROUGH;
 
     case X86Inst::kEncodingVexRmMr:
-CaseVexRmMr:
       if (isign3 == ENC_OPS2(Reg, Reg)) {
         opReg = o0.getId();
         rbReg = o1.getId();
         goto EmitVexEvexR;
       }
 
-CaseVexRmMr_AfterRegReg:
       if (isign3 == ENC_OPS2(Reg, Mem)) {
         opReg = o0.getId();
         rmRel = &o1;