Merge branch 'master' into dev-lbuf-bpu

Makefile

@@ -50,7 +50,7 @@ $(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE)
 ifeq ($(REMOTE),localhost)
 	mill chiselModule.test.runMain $(SIMTOP) -X verilog -td $(@D) --output-file $(@F) $(SIM_ARGS)
 else
-	ssh $(REMOTE) "cd $(REMOTE_PRJ_HOME) && mill chiselModule.test.runMain $(SIMTOP) -X verilog -td $(@D) --output-file $(@F) $(SIM_ARGS)"
+	ssh -tt $(REMOTE) "cd $(REMOTE_PRJ_HOME) && mill chiselModule.test.runMain $(SIMTOP) -X verilog -td $(@D) --output-file $(@F) $(SIM_ARGS)"
 endif
 
 
@@ -98,7 +98,7 @@ $(REF_SO):
 $(EMU): $(EMU_MK) $(EMU_DEPS) $(EMU_HEADERS) $(REF_SO)
 	CPPFLAGS=-DREF_SO=\\\"$(REF_SO)\\\" $(MAKE) VM_PARALLEL_BUILDS=1 -C $(dir $(EMU_MK)) -f $(abspath $(EMU_MK))
 
-SEED = -s $(shell shuf -i 1-10000 -n 1)
+SEED ?= $(shell shuf -i 1-10000 -n 1)
 
 
 # log will only be printed when (B<=GTimer<=E) && (L < loglevel)
@@ -108,9 +108,9 @@ E ?= -1
 
 emu: $(EMU)
 ifeq ($(REMOTE),localhost)
-	@$(EMU) -i $(IMAGE) $(SEED) -b $(B) -e $(E)
+	@$(EMU) -i $(IMAGE) -s $(SEED) -b $(B) -e $(E)
 else
-	ssh $(REMOTE) "cd $(REMOTE_PRJ_HOME) && $(EMU) -i $(REMOTE_PREFIX)/$(realpath $(IMAGE)) $(SEED) -b $(B) -e $(E)"
+	ssh -tt $(REMOTE) "cd $(REMOTE_PRJ_HOME) && $(EMU) -i $(REMOTE_PREFIX)/$(realpath $(IMAGE)) -s $(SEED) -b $(B) -e $(E)"
 endif
 
 cache:

debug/Makefile

@@ -20,40 +20,40 @@ cpu:
 # ------------------------------------------------------------------
 
 cputest:
-	$(MAKE) -C $(AM_HOME)/tests/cputest $(ARCH) $(EMU_ARGS) run 2>&1 | tee > cpu.log
+	$(MAKE) -C $(AM_HOME)/tests/cputest $(ARCH) $(EMU_ARGS) run 2 > cpu.log
 	cat cpu.log | grep different
 	cat cpu.log | grep IPC
 
 # bputest:
 # 	$(MAKE) -C $(AM_HOME)/tests/bputest $(ARCH) run 2>&1 | tee > bpu.log
 # 	cat bpu.log | grep different
 bputest:
-	$(MAKE) -C $(AM_HOME)/tests/bputest $(ARCH) run 2>&1 | tee > bpu.log
+	$(MAKE) -C $(AM_HOME)/tests/bputest $(ARCH) run 2 > bpu.log
 	cat bpu.log | grep Mbp
 
 amtest:
-	$(MAKE) -C $(AM_HOME)/tests/cputest $(ARCH) $(SINGLETEST) run 2>&1 | tee > test.log
+	$(MAKE) -C $(AM_HOME)/tests/cputest $(ARCH) $(SINGLETEST) run 2 > test.log
 	cat test.log | grep different
 	cat test.log | grep ISU > isu.log
 
 microbench:
-	$(MAKE) -C $(AM_HOME)/apps/microbench $(ARCH) mainargs=test run 2>&1 | tee > microbench.log
+	$(MAKE) -C $(AM_HOME)/apps/microbench $(ARCH) $(EMU_ARGS) mainargs=test run 2 > microbench.log
 	cat microbench.log | grep IPC
 
 microbench_train:
-	$(MAKE) -C $(AM_HOME)/apps/microbench $(ARCH) mainargs=train run 2>&1 | tee > microbench.log
+	$(MAKE) -C $(AM_HOME)/apps/microbench $(ARCH) $(EMU_ARGS) mainargs=train run 2 > microbench.log
 	cat microbench.log | grep IPC
 
 coremark:
-	$(MAKE) -C $(AM_HOME)/apps/coremark $(ARCH) mainargs=test run 2>&1 | tee > coremark.log
+	$(MAKE) -C $(AM_HOME)/apps/coremark $(ARCH) $(EMU_ARGS) mainargs=test run 2 > coremark.log
 	cat coremark.log | grep IPC
 
 dhrystone:
-	$(MAKE) -C $(AM_HOME)/apps/dhrystone $(ARCH) mainargs=test run 2>&1 | tee > dhrystone.log
+	$(MAKE) -C $(AM_HOME)/apps/dhrystone $(ARCH) $(EMU_ARGS) mainargs=test run 2 > dhrystone.log
 	cat dhrystone.log | grep IPC
 
 xj:
-	$(MAKE) -C $(NANOS_HOME) $(ARCH) run
+	$(MAKE) -C $(NANOS_HOME) $(ARCH) $(EMU_ARGS) run
 
 xjnemu:
 	$(MAKE) -C $(NANOS_HOME) ARCH=riscv64-nemu run
@@ -74,7 +74,7 @@ xv6-debug:
 	$(MAKE) -C $(XV6_HOME) noop 2>&1 | tee > xv6.log
 
 linux:
-	$(MAKE) -C $(BBL_LINUX_HOME) noop
+	$(MAKE) -C $(BBL_LINUX_HOME) $(EMU_ARGS) noop
 # ------------------------------------------------------------------
 # get disassembled test src
 # ------------------------------------------------------------------
@@ -90,8 +90,7 @@ disassemble-xv6:
 
 
 P = 4
-#SUITE = xiangshan.backend.exu.AluTest
-SUITE = IFUtest
+SUITE = xiangshan.backend.exu.AluTest
 
 unit-test:
 	cd .. && mill chiselModule.test.testOnly -o -s $(SUITE) -P$(P)

scripts/statistics.py

@@ -1,17 +1,79 @@
-mymap = {}
-last = ""
-
-with open("../build/XSSimTop.v", "r") as f:
-    line = f.readline()
-    cnt = 0
-    while(line):
-        if "module " in line:
-            if last!="" :
-                mymap[last] = cnt
-            last = line[6:-2]
-            cnt = 1
-        else:
-            cnt = cnt + 1
+import os
+import argparse
+
+def printMap(mp):
+    len_key = max(map(lambda s: len(s), mp.keys()))
+    len_value = max(map(lambda v: len(str(v)), mp.values()))
+    pattern = "{:<" +str(len_key) + "} {:<" +str(len_value)+ "} {:<7}%"
+    total = sum(mp.values())
+    for k,v in sorted(mp.items(), key=lambda x:x[1], reverse=True):
+        print(
+            pattern.format(k, v, round(v*100.0/total, 3))
+        )
+
+
+def analyzeVerilog(filename):
+    mymap = {}
+    last = ""
+    with open(filename, "r") as f:
         line = f.readline()
-    for k,v in mymap.items():
-        print(k, v)
+        cnt = 0
+        while(line):
+            if "module " in line:
+                if last!="" :
+                    mymap[last] = cnt
+                last = line[7:-2]
+                cnt = 1
+            else:
+                cnt = cnt + 1
+            line = f.readline()
+        mymap[last] = cnt
+        printMap(mymap)    
+
+logLevels = ['ALL', 'DEBUG', 'INFO', 'WARN', 'ERROR']
+
+def listToStr(lst):
+    acc = ''
+    for l in lst:
+        acc += '|' + str(l) if acc else str(l)
+    return acc
+
+def lineStrip(line):
+    return line.replace('\n', '')
+
+def getNumLogLines(filename, modules, ll=logLevels):
+    cmd = "grep -E '\[({0}).*\]\[time=.*\] ({1}):' {2} | wc -l".format(
+        listToStr(ll),
+        listToStr(modules),
+        filename
+    )
+    res = os.popen(cmd)
+    return int(lineStrip(res.readline()), 10)
+
+def analyzeLog(filename):
+    cmd = "grep -E '\[time=.*\]' {0} ".format(filename) + " | awk -F '(:)' {'print $1'} | awk  {'print $NF'} | sort | uniq"
+    res = os.popen(cmd)
+    modules = list(map(lineStrip, res.readlines()))
+    mymap = {}
+    for m in modules:
+        mymap[m] = getNumLogLines(filename, [m])
+    printMap(mymap)
+
+def main():
+    parser = argparse.ArgumentParser()
+    parser.add_argument("-v", "--verilogFile", help="verilog file path", type=str)
+    parser.add_argument("-l", "--logFile", help="log file path", type=str)
+    args = parser.parse_args()
+
+    if args.verilogFile:
+        analyzeVerilog(args.verilogFile)
+
+    if args.logFile:
+        analyzeLog(args.logFile)
+
+    if not args.verilogFile and not args.logFile:
+        parser.print_help()
+
+if __name__ == '__main__':
+    main()
+

src/main/scala/bus/simplebus/Crossbar.scala

@@ -1,3 +1,19 @@
+/**************************************************************************************
+* Copyright (c) 2020 Institute of Computing Technology, CAS
+* Copyright (c) 2020 University of Chinese Academy of Sciences
+* 
+* NutShell is licensed under Mulan PSL v2.
+* You can use this software according to the terms and conditions of the Mulan PSL v2. 
+* You may obtain a copy of Mulan PSL v2 at:
+*             http://license.coscl.org.cn/MulanPSL2 
+* 
+* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER 
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR 
+* FIT FOR A PARTICULAR PURPOSE.  
+*
+* See the Mulan PSL v2 for more details.  
+***************************************************************************************/
+
 package bus.simplebus
 
 import chisel3._
@@ -11,7 +27,7 @@ class SimpleBusCrossbar1toN(addressSpace: List[(Long, Long)]) extends Module {
     val out = Vec(addressSpace.length, new SimpleBusUC)
   })
 
-  val s_idle :: s_resp :: Nil = Enum(2)
+  val s_idle :: s_resp :: s_error :: Nil = Enum(3)
   val state = RegInit(s_idle)
 
   // select the output channel according to the address
@@ -22,8 +38,10 @@ class SimpleBusCrossbar1toN(addressSpace: List[(Long, Long)]) extends Module {
   val outSel = io.out(outSelIdx)
   val outSelIdxResp = RegEnable(outSelIdx, outSel.req.fire() && (state === s_idle))
   val outSelResp = io.out(outSelIdxResp)
+  val reqInvalidAddr = io.in.req.valid && !outSelVec.asUInt.orR
 
-  assert(!io.in.req.valid || outSelVec.asUInt.orR, "address decode error, bad addr = 0x%x\n", addr)
+  when(!(!io.in.req.valid || outSelVec.asUInt.orR) || !(!(io.in.req.valid && outSelVec.asUInt.andR))){printf("[ERROR] bad addr %x, time %d\n", addr, GTimer())}
+  // assert(!io.in.req.valid || outSelVec.asUInt.orR, "address decode error, bad addr = 0x%x\n", addr)
   assert(!(io.in.req.valid && outSelVec.asUInt.andR), "address decode error, bad addr = 0x%x\n", addr)
 
   // bind out.req channel
@@ -34,14 +52,19 @@ class SimpleBusCrossbar1toN(addressSpace: List[(Long, Long)]) extends Module {
   }}
 
   switch (state) {
-    is (s_idle) { when (outSel.req.fire()) { state := s_resp } }
+    is (s_idle) { 
+      when (outSel.req.fire()) { state := s_resp } 
+      when (reqInvalidAddr) { state := s_error } 
+    }
     is (s_resp) { when (outSelResp.resp.fire()) { state := s_idle } }
+    is (s_error) { when(io.in.resp.fire()){ state := s_idle } }
   }
 
-  io.in.resp.valid := outSelResp.resp.fire()
+  io.in.resp.valid := outSelResp.resp.fire() || state === s_error
   io.in.resp.bits <> outSelResp.resp.bits
+  // io.in.resp.bits.exc.get := state === s_error
   outSelResp.resp.ready := io.in.resp.ready
-  io.in.req.ready := outSel.req.ready
+  io.in.req.ready := outSel.req.ready || reqInvalidAddr
 
   Debug() {
     when (state === s_idle && io.in.req.valid) {

src/main/scala/system/SoC.scala

@@ -63,7 +63,7 @@ class XSSoc(implicit val p: XSConfig) extends Module with HasSoCParameter {
   xsCore.io.imem.coh.req.bits := DontCare
 
   val addrSpace = List(
-    (0x40000000L, 0x08000000L), // external devices
+    (0x40000000L, 0x40000000L), // external devices
     (0x38000000L, 0x00010000L)  // CLINT
   )
   val mmioXbar = Module(new SimpleBusCrossbar1toN(addrSpace))

src/main/scala/utils/LogUtils.scala

@@ -28,6 +28,9 @@ object XSLog {
     if(generateLog){
       when (cond && logEnable) {
         printf((if (prefix) commonInfo else p"") + pable)
+        if (debugLevel >= XSLogLevel.ERROR) {
+          assert(false.B)
+        }
       }
     }
   }

src/main/scala/xiangshan/Bundle.scala

@@ -11,12 +11,12 @@ class FetchPacket extends XSBundle {
   val instrs = Vec(FetchWidth, UInt(32.W))
   val mask = UInt((FetchWidth*2).W)
   val pc = UInt(VAddrBits.W) // the pc of first inst in the fetch group
-  val pnpc = Vec(FetchWidth, UInt(VAddrBits.W))
-  val hist = Vec(FetchWidth, UInt(HistoryLength.W))
+  val pnpc = Vec(FetchWidth*2, UInt(VAddrBits.W))
+  val hist = Vec(FetchWidth*2, UInt(HistoryLength.W))
   // val btbVictimWay = UInt(log2Up(BtbWays).W)
-  val predCtr = Vec(FetchWidth, UInt(2.W))
-  val btbHitWay = Bool()
-  val tageMeta = Vec(FetchWidth, (new TageMeta))
+  val predCtr = Vec(FetchWidth*2, UInt(2.W))
+  val btbHit = Vec(FetchWidth*2, Bool())
+  val tageMeta = Vec(FetchWidth*2, (new TageMeta))
   val rasSp = UInt(log2Up(RasSize).W)
   val rasTopCtr = UInt(8.W)
   val branchInfo = Vec(FetchWidth,Bool())
@@ -48,30 +48,31 @@ class BranchPrediction extends XSBundle {
   val redirect = Bool()
 
   // mask off all the instrs after the first redirect instr
-  val instrValid = Vec(FetchWidth, Bool())
+  val instrValid = Vec(FetchWidth*2, Bool())
   // target of the first redirect instr in a fetch package
   val target = UInt(VAddrBits.W)
-
+  val lateJump = Bool()
   // save these info in brq!
   // global history of each valid(or uncancelled) instruction, excluding branch's own prediction result
-  val hist = Vec(FetchWidth, UInt(HistoryLength.W))
+  val hist = Vec(FetchWidth*2, UInt(HistoryLength.W))
   // victim way when updating btb
   // val btbVictimWay = UInt(log2Up(BtbWays).W)
   // 2-bit saturated counter 
-  val predCtr = Vec(FetchWidth, UInt(2.W))
-  val btbHitWay = Bool()
+  val predCtr = Vec(FetchWidth*2, UInt(2.W))
+  val btbHit = Vec(FetchWidth*2, Bool())
   // tage meta info
-  val tageMeta = Vec(FetchWidth, (new TageMeta))
+  val tageMeta = Vec(FetchWidth*2, (new TageMeta))
   // ras checkpoint, only used in Stage3
   val rasSp = UInt(log2Up(RasSize).W)
   val rasTopCtr = UInt(8.W)
 }
 
 // Save predecode info in icache
 class Predecode extends XSBundle {
-  val mask = UInt(FetchWidth.W)
-  val fuTypes = Vec(FetchWidth, FuType())
-  val fuOpTypes = Vec(FetchWidth, FuOpType())
+  val mask = UInt((FetchWidth*2).W)
+  val isRVC = Vec(FetchWidth*2, Bool())
+  val fuTypes = Vec(FetchWidth*2, FuType())
+  val fuOpTypes = Vec(FetchWidth*2, FuOpType())
 }
 
 // Dequeue DecodeWidth insts from Ibuffer
@@ -83,7 +84,7 @@ class CtrlFlow extends XSBundle {
   val hist = UInt(HistoryLength.W)
   // val btbVictimWay = UInt(log2Up(BtbWays).W)
   val btbPredCtr = UInt(2.W)
-  val btbHitWay = Bool()
+  val btbHit = Bool()
   val tageMeta = new TageMeta
   val rasSp = UInt(log2Up(RasSize).W)
   val rasTopCtr = UInt(8.W)
@@ -130,14 +131,15 @@ class Redirect extends XSBundle {
   val brTarget = UInt(VAddrBits.W)
   val brTag = new BrqPtr
   val btbType = UInt(2.W)
+  val isRVC = Bool()
   //val isCall = Bool()
   val taken = Bool()
   val hist = UInt(HistoryLength.W)
   val tageMeta = new TageMeta
-  val fetchIdx = UInt(log2Up(FetchWidth).W)
+  val fetchIdx = UInt(log2Up(FetchWidth*2).W)
   // val btbVictimWay = UInt(log2Up(BtbWays).W)
   val btbPredCtr = UInt(2.W)
-  val btbHitWay = Bool()
+  val btbHit = Bool()
   val rasSp = UInt(log2Up(RasSize).W)
   val rasTopCtr = UInt(8.W)
   val isException = Bool()
@@ -180,7 +182,8 @@ class ExuIO extends XSBundle {
   val in = Flipped(DecoupledIO(new ExuInput))
   val redirect = Flipped(ValidIO(new Redirect))
   val out = DecoupledIO(new ExuOutput)
-
+  // for csr
+  val exception = Flipped(ValidIO(new MicroOp))
   // for Lsu
   val dmem = new SimpleBusUC
   val scommit = Input(UInt(3.W))
@@ -196,5 +199,5 @@ class FrontendToBackendIO extends XSBundle {
   val cfVec = Vec(DecodeWidth, DecoupledIO(new CtrlFlow))
   // from backend
   val redirectInfo = Input(new RedirectInfo)
-  val commits = Vec(CommitWidth, Flipped(ValidIO(new RoqCommit))) // update branch pred
+  val inOrderBrInfo = Input(new RedirectInfo)
 }