Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
README.md		README.md
alu.v		alu.v
clock_gen.v		clock_gen.v
dff.v		dff.v
instruction_memory.v		instruction_memory.v
prefix_adder.v		prefix_adder.v
registers.v		registers.v
riscv_defs.v		riscv_defs.v

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riscv-cpu

A simple RV-32 CPU in verilog.