CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…

A port of circuitikz to Typst using CeTZ!

Verilator open-source SystemVerilog simulator and lint system

Prefix tree adder space exploration library

A new Citra fork

Code at the speed of thought – Zed is a high-performance, multiplayer code editor from the creators of Atom and Tree-sitter.

Instruction Set Generator initially contributed by Futurewei

A powerful thumbnail manager for Python

A Linux-capable RISC-V multicore for and by the world

Magic VLSI Layout Tool

Library Characterization Environment - Open source tool for Cell Library Characterization

A User-Focused Photo & File Management System

The home of moss (system state and package manager) and boulder (moss format build tool)

GNU toolchain for RISC-V, including GCC

Sail RISC-V model

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Serpent OS Package Recipes

Picard is a cross-platform music tagger powered by the MusicBrainz database

Latex lua-written plugin for Micro editor.

This repo collates my projects with the Alchitry AU FPGA

An open-source static random access memory (SRAM) compiler.

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format …

Universal utility for programming FPGA

Spike, a RISC-V ISA Simulator

RISC-V Instruction Set Manual

PicoRV32 - A Size-Optimized RISC-V CPU

Experimental flows using nextpnr for Xilinx devices

Documenting the Xilinx 7-series bit-stream format.