《动手学深度学习》：面向中文读者、能运行、可讨论。中英文版被70多个国家的500多所大学用于教学。

基于verilog实现了ISP图像处理IP

Image Signal Processor

YOLOv5 🚀 in PyTorch > ONNX > CoreML > TFLite

Ultralytics YOLO11 🚀

2023集创赛紫光同创杯一等奖项目

A camera ISP (image signal processor) pipeline that contains modules with simple to complex algorithms implemented at the application level.

For Notion,OneNote,Bear,Yuque,Joplin。Clip anything to anywhere

Verilog I2C interface for FPGA implementation

kintex7 ov13850 fpga mipi camera

Open Source 4k CSI-2 Rx core for Xilinx FPGAs

https://en.wikipedia.org/wiki/CAN_bus

https://en.wikipedia.org/wiki/CAN_bus

An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。

An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。

MIPI CSI-2 Camera Sensor Receiver verilog HDL implementation For any generic FPGA. Tested with IMX219 on Lattice MachXO3LF. 2Gbps UVC Video Stream Over USB 3.0 with Cypress FX3. This is now Legacy …

An CAN bus Controller implemented in Verilog

TDC Hybrid Counter FPGA

Implementation of tappped delay line TDC on FPGA

Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核

MLNLP: This repository is a collection of AI top conferences papers (e.g. ACL, EMNLP, NAACL, COLING, AAAI, IJCAI, ICLR, NeurIPS, and ICML) with open resource code

Transformer with Untied Positional Encoding (TUPE). Code of paper "Rethinking Positional Encoding in Language Pre-training". Improve existing models like BERT.

使用Bert完成实体之间关系抽取

Pytorch BERT-BiLSTM-CRF For NER

A Python framework for sequence labeling evaluation(named-entity recognition, pos tagging, etc...)

Easy Natural Language Processing

该repo可用于将OntoNotes-5.0转换为Conll格式

该repo可用于将OntoNotes-5.0转换为Conll格式