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[SYCL][Doc] Release notes for Mar'25 release #18469

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Some general comments: a new structure is used this time. We have less top-level categories, but more sub-categories which group items based on some feature/activity/area.

Motivation for that is because "Improvements & Bug Fixes -> Feature Name" is expected to be more interesting and useful for an end user, than a one huge list of Bug Fixes for everything.

We still have some kind of fallback section "all other bugfixes", but at least it is not that huge.

Any feedback on the new structure is appreciated


## New Features

### Runtime compilation of SYCL code
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@intel/dpcpp-kernel-fusion-reviewers, tagging you here to review this section

[in the extension specification](https://github.com/intel/llvm/blob/b23d69e2c3fda1d69351137991897c96bf6a586d/sycl/doc/extensions/experimental/sycl_ext_oneapi_kernel_compiler.asciidoc#non-normative-implementation-notes-for-dpc). intel/llvm#17307,
intel/llvm#17459

### SYCL graphs
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@intel/sycl-graphs-reviewers, tagging you to review this and other graph-related sections

native runtimes into graphs built using `sycl_ext_oneapi_graph` extension.
intel/llvm#16871

### Bindless images
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@intel/bindless-images-reviewers, tagging you to review this and other sections related to bindless images

`gather_image` device built-in function. The implementation was only done for
CUDA backend so far. intel/llvm#17322

### Native CPU Device
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@intel/dpcpp-nativecpu-reviewers, tagging you for review here


### KHR extensions

Please note that KHR extensions are being specified and released by Khronos
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@gmlueck, tagging you here for feedback. I'm on a verge about whether or not we should mention implementation of unfinished KHRs in our release notes. The proposed wording is to do document them to share awareness/give some insights, but at the same time they may not be ready to be used yet.

- Improved support for sub-groups by updating version of OneAPI Construction
Kit. intel/llvm#16785

### Matrix
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@intel/sycl-matrix-reviewers, tagging you for review here

extension specification and implementation to support Intel Xeon processors
codenamed Diamond Rapids. intel/llvm#16543

### Optimizations of SYCL Runtime
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Tagging @intel/llvm-reviewers-runtime for review

to see the list of working and non-working examples.


43ee65117935 [UR] Fix potential deadlock in the WaitEvent path of CmdBuffers (#16697)
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@intel/unified-runtime-reviewers, I haven't looked into those items at all. My plan is to drop them completely, but if you know of something that is worth mentioning, then please let me know and I will preserve those items.

spec change (KhronosGroup/SYCL-Docs#704). intel/llvm#15890
- Implemented `swizzle` method for swizzles. intel/llvm#16353

### Other changes in SYCL Compiler
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Tagging @intel/dpcpp-clang-driver-reviewers, @intel/llvm-reviewers-cuda, @intel/dpcpp-tools-reviewers, @intel/unified-runtime-reviewers, tagging you to have a glance over this generic section

- Fixed debug information for kernels that use global offest on HIP & CUDA
backends. intel/llvm#16963

### Other changes in SYCL Library
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@intel/unified-runtime-reviewers, @intel/llvm-reviewers-cuda, tagging you to have a glance over this generic section

@AlexeySachkov AlexeySachkov marked this pull request as ready for review May 14, 2025 16:49
@AlexeySachkov AlexeySachkov requested review from tfzhu and a team as code owners May 14, 2025 16:49
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General CUDA/HIP entries LGTM

`rint` for HIP targets. intel/lllvm#16373
- Improved check for unsupported data types to actually rely on target
information instead of hardcoded knowledge. For example, this allows 128-bit
integeres to be used in device code when targeting CUDA backend.
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Suggested change
integeres to be used in device code when targeting CUDA backend.
integers to be used in device code when targeting CUDA backend.

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