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Merge upstream/master into tmp-backend-merge-master
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huxuan0307 committed Oct 11, 2023
2 parents a99e452 + 7f37d55 commit 4b0d80d
Showing 193 changed files with 9,500 additions and 4,735 deletions.
6 changes: 6 additions & 0 deletions .github/workflows/check_verilog.py
Original file line number Diff line number Diff line change
@@ -9,6 +9,7 @@ def err(line, loc, msg):
if __name__ == "__main__":
in_decode = False
in_dispatch = False
in_miss_entry = False
in_sync_always = False
always_depth = 0
line_number = 0
@@ -20,13 +21,18 @@ def err(line, loc, msg):
in_decode = True
elif "module Dispatch" in line:
in_dispatch = True
elif "module MissEntry" in line:
in_miss_entry = True
elif "endmodule" in line:
in_decode = False
in_dispatch = False
in_miss_entry = False
elif in_decode and "_pc" in line:
err(line, line_number, "PC should not be in decode!!!\n")
elif in_dispatch and "_lsrc" in line:
err(line, line_number, "lsrc should not be in dispatch!!!\n")
elif in_miss_entry and "refill_data_raw" in line:
err(line, line_number, "refill_data_raw should not be in MissEntry!!!\n")
if "always @(posedge clock) begin" in line:
in_sync_always = True
if in_sync_always:
16 changes: 13 additions & 3 deletions Makefile
Original file line number Diff line number Diff line change
@@ -48,6 +48,16 @@ endif
override SIM_ARGS += --with-dramsim3
endif

# run emu with chisel-db
ifeq ($(WITH_CHISELDB),1)
override SIM_ARGS += --with-chiseldb
endif

# run emu with chisel-db
ifeq ($(WITH_ROLLINGDB),1)
override SIM_ARGS += --with-rollingdb
endif

# dynamic switch CONSTANTIN
ifeq ($(WITH_CONSTANTIN),0)
$(info disable WITH_CONSTANTIN)
@@ -131,7 +141,7 @@ clean:

init:
git submodule update --init
cd rocket-chip && git submodule update --init api-config-chipsalliance hardfloat
cd rocket-chip && git submodule update --init cde hardfloat

bump:
git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master"
@@ -143,10 +153,10 @@ idea:
mill -i mill.scalalib.GenIdea/idea

# verilator simulation
emu:
emu: sim-verilog
$(MAKE) -C ./difftest emu SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES)

emu-run:
emu-run: emu
$(MAKE) -C ./difftest emu-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES)

# vcs simulation
232 changes: 121 additions & 111 deletions build.sc
Original file line number Diff line number Diff line change
@@ -14,162 +14,158 @@
* See the Mulan PSL v2 for more details.
***************************************************************************************/

import os.Path
import mill._
import scalalib._
import publish._
import coursier.maven.MavenRepository
import $file.`rocket-chip`.common
import $file.`rocket-chip`.`api-config-chipsalliance`.`build-rules`.mill.build
import $file.`rocket-chip`.cde.common
import $file.`rocket-chip`.hardfloat.build
import $file.huancun.common
import $file.coupledL2.common

object ivys {
val sv = "2.12.13"
val chisel3 = ivy"edu.berkeley.cs::chisel3:3.5.0"
val chisel3Plugin = ivy"edu.berkeley.cs:::chisel3-plugin:3.5.0"
val chiseltest = ivy"edu.berkeley.cs::chiseltest:0.5.2"
val chiselCirct = ivy"com.sifive::chisel-circt:0.6.0"
val scalatest = ivy"org.scalatest::scalatest:3.2.2"
val macroParadise = ivy"org.scalamacros:::paradise:2.1.1"
}

trait XSModule extends ScalaModule with PublishModule {
val defaultScalaVersion = "2.13.10"

// override this to use chisel from source
def chiselOpt: Option[PublishModule] = None
val defaultVersions = Map(
"chisel" -> ivy"edu.berkeley.cs::chisel3:3.6.0",
"chisel-plugin" -> ivy"edu.berkeley.cs:::chisel3-plugin:3.6.0",
"chiseltest" -> ivy"edu.berkeley.cs::chiseltest:0.6.2",
)

override def scalaVersion = ivys.sv
trait HasChisel extends ScalaModule {
def chiselModule: Option[ScalaModule] = None

override def compileIvyDeps = Agg(ivys.macroParadise)
def chiselPluginJar: T[Option[PathRef]] = None

override def scalacPluginIvyDeps = Agg(ivys.macroParadise, ivys.chisel3Plugin)
def chiselIvy: Option[Dep] = Some(defaultVersions("chisel"))

override def scalacOptions = Seq("-Xsource:2.11")
def chiselPluginIvy: Option[Dep] = Some(defaultVersions("chisel-plugin"))

override def ivyDeps = (if(chiselOpt.isEmpty) Agg(ivys.chisel3) else Agg.empty[Dep]) ++ Agg(ivys.chiselCirct)
override def scalaVersion = defaultScalaVersion

override def moduleDeps = Seq() ++ chiselOpt
override def scalacOptions = super.scalacOptions() ++
Agg("-language:reflectiveCalls", "-Ymacro-annotations", "-Ytasty-reader")

def publishVersion = "0.0.1"
override def ivyDeps = super.ivyDeps() ++ Agg(chiselIvy.get)

// TODO: fix this
def pomSettings = PomSettings(
description = "XiangShan",
organization = "",
url = "https://github.com/OpenXiangShan/XiangShan",
licenses = Seq(License.`Apache-2.0`),
versionControl = VersionControl.github("OpenXiangShan", "XiangShan"),
developers = Seq.empty
)
override def scalacPluginIvyDeps = super.scalacPluginIvyDeps() ++ Agg(chiselPluginIvy.get)
}

object rocketchip extends `rocket-chip`.common.CommonRocketChip {
object rocketchip extends RocketChip

trait RocketChip
extends millbuild.`rocket-chip`.common.RocketChipModule
with SbtModule with HasChisel {
def scalaVersion: T[String] = T(defaultScalaVersion)

override def millSourcePath = os.pwd / "rocket-chip"

val rcPath = os.pwd / "rocket-chip"
def macrosModule = macros

override def scalaVersion = ivys.sv
def hardfloatModule = hardfloat

override def scalacOptions = Seq("-Xsource:2.11")
def cdeModule = cde

override def millSourcePath = rcPath
def mainargsIvy = ivy"com.lihaoyi::mainargs:0.5.0"

object configRocket extends `rocket-chip`.`api-config-chipsalliance`.`build-rules`.mill.build.config with PublishModule {
override def millSourcePath = rcPath / "api-config-chipsalliance" / "design" / "craft"
def json4sJacksonIvy = ivy"org.json4s::json4s-jackson:4.0.5"

override def scalaVersion = T {
rocketchip.scalaVersion()
}
object macros extends Macros

override def pomSettings = T {
rocketchip.pomSettings()
}
trait Macros
extends millbuild.`rocket-chip`.common.MacrosModule
with SbtModule {

override def publishVersion = T {
rocketchip.publishVersion()
}
def scalaVersion: T[String] = T(defaultScalaVersion)

def scalaReflectIvy = ivy"org.scala-lang:scala-reflect:${defaultScalaVersion}"
}

object hardfloatRocket extends `rocket-chip`.hardfloat.build.hardfloat {
override def millSourcePath = rcPath / "hardfloat"
object hardfloat extends Hardfloat

trait Hardfloat
extends millbuild.`rocket-chip`.hardfloat.common.HardfloatModule with HasChisel {

override def scalaVersion = T {
rocketchip.scalaVersion()
}
def scalaVersion: T[String] = T(defaultScalaVersion)

def chisel3IvyDeps = if(chisel3Module.isEmpty) Agg(
common.getVersion("chisel3")
) else Agg.empty[Dep]
override def millSourcePath = os.pwd / "rocket-chip" / "hardfloat" / "hardfloat"

def chisel3PluginIvyDeps = Agg(common.getVersion("chisel3-plugin", cross=true))
}

def hardfloatModule = hardfloatRocket
object cde extends CDE

def configModule = configRocket
trait CDE extends millbuild.`rocket-chip`.cde.common.CDEModule with ScalaModule {

def scalaVersion: T[String] = T(defaultScalaVersion)

override def millSourcePath = os.pwd / "rocket-chip" / "cde" / "cde"
}
}

object huancun extends XSModule with SbtModule {
object utility extends SbtModule with HasChisel {

override def millSourcePath = os.pwd / "huancun"
override def millSourcePath = os.pwd / "utility"

override def moduleDeps = super.moduleDeps ++ Seq(
rocketchip,
utility
rocketchip
)

}

object coupledL2 extends XSModule with SbtModule {
object yunsuan extends XSModule with SbtModule {

override def millSourcePath = os.pwd / "coupledL2"
override def millSourcePath = os.pwd / "yunsuan"

override def moduleDeps = super.moduleDeps ++ Seq(
rocketchip,
huancun,
utility
)
}

object difftest extends XSModule with SbtModule {
override def millSourcePath = os.pwd / "difftest"
object huancun extends millbuild.huancun.common.HuanCunModule with SbtModule with HasChisel {

override def millSourcePath = os.pwd / "huancun"

def rocketModule: ScalaModule = rocketchip

def utilityModule: ScalaModule = utility

}

object yunsuan extends XSModule with SbtModule {
override def millSourcePath = os.pwd / "yunsuan"
object coupledL2 extends millbuild.coupledL2.common.CoupledL2Module with SbtModule with HasChisel {

override def millSourcePath = os.pwd / "coupledL2"

def rocketModule: ScalaModule = rocketchip

def utilityModule: ScalaModule = utility

def huancunModule: ScalaModule = huancun

}

object fudian extends XSModule with SbtModule
object difftest extends SbtModule with HasChisel {

object utility extends XSModule with SbtModule {
override def millSourcePath = os.pwd / "difftest"

override def millSourcePath = os.pwd / "utility"
}

object fudian extends SbtModule with HasChisel {

override def millSourcePath = os.pwd / "fudian"

override def moduleDeps = super.moduleDeps ++ Seq(
rocketchip
)
}

// extends this trait to use XiangShan in other projects
trait CommonXiangShan extends XSModule with SbtModule { m =>
trait XiangShanModule extends ScalaModule {

// module deps
def rocketModule: PublishModule
def difftestModule: PublishModule
def huancunModule: PublishModule
def coupledL2Module: PublishModule
def yunsuanModule: PublishModule
def fudianModule: PublishModule
def utilityModule: PublishModule
def rocketModule: ScalaModule

override def millSourcePath = os.pwd
def difftestModule: ScalaModule

override def forkArgs = Seq("-Xmx64G", "-Xss256m")
def huancunModule: ScalaModule

val resourcesPATH = os.pwd.toString() + "/src/main/resources"
val envPATH = sys.env("PATH") + ":" + resourcesPATH
override def forkEnv = Map("PATH" -> envPATH)
def coupledL2Module: ScalaModule

override def ivyDeps = super.ivyDeps() ++ Seq(ivys.chiseltest)
def fudianModule: ScalaModule

def utilityModule: ScalaModule

def yunsuanModule: PublishModule

override def moduleDeps = super.moduleDeps ++ Seq(
rocketModule,
@@ -178,29 +174,43 @@ trait CommonXiangShan extends XSModule with SbtModule { m =>
coupledL2Module,
yunsuanModule,
fudianModule,
utilityModule
utilityModule,
)

object test extends SbtModuleTests with TestModule.ScalaTest {
val resourcesPATH = os.pwd.toString() + "/src/main/resources"
val envPATH = sys.env("PATH") + ":" + resourcesPATH

override def forkEnv = Map("PATH" -> envPATH)

override def ivyDeps = super.ivyDeps() ++ Seq(ivys.chiseltest)
}

object XiangShan extends XiangShanModule with SbtModule with HasChisel {

override def millSourcePath = millOuterCtx.millSourcePath

def rocketModule = rocketchip

def difftestModule = difftest

def huancunModule = huancun

override def forkArgs = m.forkArgs
def coupledL2Module = coupledL2

def fudianModule = fudian

def utilityModule = utility

override def forkArgs = Seq("-Xmx20G", "-Xss256m")

object test extends SbtModuleTests with TestModule.ScalaTest {
override def forkArgs = XiangShan.forkArgs

override def forkEnv = m.forkEnv

override def ivyDeps = super.ivyDeps() ++ Agg(
ivys.scalatest
defaultVersions("chiseltest"),
)

}

}

object XiangShan extends CommonXiangShan {
override def rocketModule = rocketchip
override def difftestModule = difftest
override def huancunModule = huancun
override def coupledL2Module = coupledL2
override def yunsuanModule = yunsuan
override def fudianModule = fudian
override def utilityModule = utility
}
2 changes: 1 addition & 1 deletion coupledL2
Submodule coupledL2 updated 50 files
+4 −4 .github/workflows/main.yml
+3 −0 .gitignore
+1 −1 .mill-version
+1 −1 HuanCun
+1 −6 Makefile
+43 −60 build.sc
+13 −0 common.sc
+1 −1 rocket-chip
+16 −76 src/main/scala/coupledL2/AcquireUnit.scala
+71 −68 src/main/scala/coupledL2/Common.scala
+39 −29 src/main/scala/coupledL2/CoupledL2.scala
+4 −4 src/main/scala/coupledL2/CustomL1Hint.scala
+6 −7 src/main/scala/coupledL2/DataStorage.scala
+148 −114 src/main/scala/coupledL2/Directory.scala
+240 −144 src/main/scala/coupledL2/GrantBuffer.scala
+0 −259 src/main/scala/coupledL2/GrantBufferFIFO.scala
+16 −38 src/main/scala/coupledL2/L2Param.scala
+265 −107 src/main/scala/coupledL2/MSHR.scala
+2 −2 src/main/scala/coupledL2/MSHRBuffer.scala
+31 −30 src/main/scala/coupledL2/MSHRCtl.scala
+191 −180 src/main/scala/coupledL2/MainPipe.scala
+5 −5 src/main/scala/coupledL2/ProbeQueue.scala
+21 −4 src/main/scala/coupledL2/RefillUnit.scala
+50 −52 src/main/scala/coupledL2/RequestArb.scala
+66 −48 src/main/scala/coupledL2/RequestBuffer.scala
+58 −67 src/main/scala/coupledL2/SinkA.scala
+112 −0 src/main/scala/coupledL2/SinkB.scala
+57 −17 src/main/scala/coupledL2/SinkC.scala
+40 −27 src/main/scala/coupledL2/Slice.scala
+11 −11 src/main/scala/coupledL2/SourceB.scala
+133 −118 src/main/scala/coupledL2/SourceC.scala
+166 −22 src/main/scala/coupledL2/TopDownMonitor.scala
+83 −8 src/main/scala/coupledL2/debug/Monitor.scala
+15 −14 src/main/scala/coupledL2/prefetch/BestOffsetPrefetch.scala
+27 −1 src/main/scala/coupledL2/prefetch/PrefetchParameters.scala
+7 −6 src/main/scala/coupledL2/prefetch/PrefetchReceiver.scala
+66 −24 src/main/scala/coupledL2/prefetch/Prefetcher.scala
+275 −0 src/main/scala/coupledL2/prefetch/TemporalPrefetch.scala
+223 −0 src/main/scala/coupledL2/utils/L2PerfCounterUtils.scala
+1 −2 src/main/scala/coupledL2/utils/Replacer.scala
+1 −1 src/main/scala/coupledL2/utils/SRAMTemplate.scala
+3 −3 src/main/scala/coupledL2/utils/SRAMWrapper.scala
+5 −5 src/main/scala/coupledL2/utils/Throttle.scala
+0 −137 src/main/scala/coupledL2/utils/XSPerfAccumulate.scala
+2 −2 src/test/scala/TestProbeQueue.scala
+99 −15 src/test/scala/TestTop.scala
+1 −1 src/test/scala/TestWritebackQueue.scala
+1 −1 src/test/scala/tltest/TLCAgent.scala
+20 −20 src/test/scala/tltest/TLCScalaMessage.scala
+1 −1 utility
2 changes: 1 addition & 1 deletion difftest
Submodule difftest updated 74 files
+174 −52 .github/workflows/main.yml
+0 −0 .gitmodules
+2 −0 .mill-version
+4 −4 LICENSE
+130 −26 Makefile
+114 −38 README.md
+33 −32 build.sc
+24 −49 config/config.h
+0 −51 config/verilator.mk
+0 −135 doc/example-nutshell.md
+0 −242 doc/example-xiangshan.md
+111 −0 scripts/coverage/coverage.py
+316 −0 scripts/coverage/statistics.py
+53 −0 scripts/coverage/vtransform.py
+61 −0 src/main/scala/Batch.scala
+220 −0 src/main/scala/Bundles.scala
+216 −0 src/main/scala/DPIC.scala
+325 −252 src/main/scala/Difftest.scala
+0 −59 src/main/scala/DifftestMain.scala
+113 −0 src/main/scala/Merge.scala
+254 −0 src/main/scala/common/Mem.scala
+63 −15 src/test/csrc/common/common.cpp
+19 −7 src/test/csrc/common/common.h
+17 −9 src/test/csrc/common/compress.cpp
+5 −3 src/test/csrc/common/compress.h
+229 −0 src/test/csrc/common/coverage.cpp
+253 −0 src/test/csrc/common/coverage.h
+2 −19 src/test/csrc/common/device.cpp
+2 −3 src/test/csrc/common/device.h
+39 −0 src/test/csrc/common/dut.cpp
+146 −0 src/test/csrc/common/dut.h
+4 −5 src/test/csrc/common/flash.cpp
+2 −2 src/test/csrc/common/flash.h
+9 −3 src/test/csrc/common/golden.cpp
+5 −5 src/test/csrc/common/golden.h
+18 −19 src/test/csrc/common/keyboard.cpp
+3 −3 src/test/csrc/common/lightsss.h
+2 −2 src/test/csrc/common/macro.h
+69 −0 src/test/csrc/common/main.cpp
+258 −50 src/test/csrc/common/ram.cpp
+181 −10 src/test/csrc/common/ram.h
+2 −2 src/test/csrc/common/sdcard.cpp
+2 −2 src/test/csrc/common/sdcard.h
+2 −2 src/test/csrc/common/uart.cpp
+2 −2 src/test/csrc/common/vga.cpp
+360 −332 src/test/csrc/difftest/difftest.cpp
+208 −343 src/test/csrc/difftest/difftest.h
+82 −0 src/test/csrc/difftest/difftrace.cpp
+31 −0 src/test/csrc/difftest/difftrace.h
+21 −16 src/test/csrc/difftest/goldenmem.cpp
+11 −13 src/test/csrc/difftest/goldenmem.h
+0 −522 src/test/csrc/difftest/interface.cpp
+0 −583 src/test/csrc/difftest/interface.h
+221 −161 src/test/csrc/difftest/refproxy.cpp
+204 −38 src/test/csrc/difftest/refproxy.h
+3 −3 src/test/csrc/plugin/runahead/memdep.cpp
+2 −2 src/test/csrc/plugin/runahead/memdep.h
+30 −30 src/test/csrc/plugin/runahead/runahead.cpp
+5 −5 src/test/csrc/plugin/runahead/runahead.h
+25 −25 src/test/csrc/plugin/spikedasm/spikedasm.cpp
+2 −3 src/test/csrc/plugin/spikedasm/spikedasm.h
+6 −9 src/test/csrc/vcs/vcs_main.cpp
+520 −249 src/test/csrc/verilator/emu.cpp
+57 −75 src/test/csrc/verilator/emu.h
+0 −60 src/test/csrc/verilator/main.cpp
+3 −3 src/test/csrc/verilator/snapshot.cpp
+3 −3 src/test/csrc/verilator/snapshot.h
+56 −0 src/test/scala/DifftestMain.scala
+2 −2 src/test/vsrc/common/assert.v
+2 −3 src/test/vsrc/common/ram.v
+2 −2 src/test/vsrc/common/ref.v
+6 −3 src/test/vsrc/vcs/top.v
+39 −23 vcs.mk
+54 −89 verilator.mk
2 changes: 1 addition & 1 deletion huancun
Submodule huancun updated 59 files
+2 −2 .github/workflows/main.yml
+3 −0 .gitignore
+1 −1 .mill-version
+4 −5 Makefile
+1 −1 Utility
+40 −64 build.sc
+12 −0 common.sc
+1 −1 rocket-chip
+8 −1 src/main/resources/STD_CLKGT_func.v
+3 −3 src/main/scala/huancun/BankedXbar.scala
+14 −14 src/main/scala/huancun/BaseDirectory.scala
+2 −1 src/main/scala/huancun/BaseMSHR.scala
+3 −2 src/main/scala/huancun/BaseSinkC.scala
+9 −19 src/main/scala/huancun/Common.scala
+4 −4 src/main/scala/huancun/CtrlUnit.scala
+10 −10 src/main/scala/huancun/DataStorage.scala
+13 −31 src/main/scala/huancun/HCCacheParameters.scala
+33 −25 src/main/scala/huancun/HuanCun.scala
+10 −10 src/main/scala/huancun/MSHRAlloc.scala
+5 −5 src/main/scala/huancun/RefillBuffer.scala
+18 −18 src/main/scala/huancun/RequestBuffer.scala
+11 −9 src/main/scala/huancun/SinkA.scala
+3 −1 src/main/scala/huancun/SinkB.scala
+3 −3 src/main/scala/huancun/SinkD.scala
+2 −2 src/main/scala/huancun/SinkE.scala
+8 −5 src/main/scala/huancun/Slice.scala
+6 −5 src/main/scala/huancun/SourceA.scala
+1 −1 src/main/scala/huancun/SourceB.scala
+6 −5 src/main/scala/huancun/SourceC.scala
+10 −6 src/main/scala/huancun/SourceD.scala
+1 −1 src/main/scala/huancun/SourceE.scala
+9 −11 src/main/scala/huancun/TopDownMonitor.scala
+2 −2 src/main/scala/huancun/debug/DirectoryLogger.scala
+3 −3 src/main/scala/huancun/inclusive/Directory.scala
+12 −12 src/main/scala/huancun/inclusive/MSHR.scala
+13 −13 src/main/scala/huancun/inclusive/SinkC.scala
+19 −19 src/main/scala/huancun/noninclusive/Directory.scala
+48 −31 src/main/scala/huancun/noninclusive/MSHR.scala
+7 −5 src/main/scala/huancun/noninclusive/ProbeHelper.scala
+18 −13 src/main/scala/huancun/noninclusive/SinkC.scala
+19 −17 src/main/scala/huancun/noninclusive/SliceCtrl.scala
+11 −10 src/main/scala/huancun/prefetch/BestOffsetPrefetch.scala
+1 −1 src/main/scala/huancun/prefetch/PrefetchParameters.scala
+8 −3 src/main/scala/huancun/prefetch/PrefetchReceiver.scala
+24 −2 src/main/scala/huancun/prefetch/Prefetcher.scala
+3 −3 src/main/scala/huancun/utils/ResetGen.scala
+1 −1 src/main/scala/huancun/utils/SRAMTemplate.scala
+3 −3 src/main/scala/huancun/utils/SRAMWrapper.scala
+5 −5 src/main/scala/huancun/utils/Throttle.scala
+20 −29 src/main/scala/huancun/utils/XSPerfAccumulate.scala
+3 −2 src/test/scala/huancun/ExampleSystem.scala
+13 −9 src/test/scala/huancun/FakeClient.scala
+1 −1 src/test/scala/huancun/L2Tester.scala
+1 −1 src/test/scala/huancun/TLDebugNode.scala
+62 −21 src/test/scala/huancun/TestTop.scala
+1 −1 src/test/scala/huancun/tlctest/DirConflictTester.scala
+3 −2 src/test/scala/huancun/tlctest/TLCTest.scala
+1 −1 src/test/scala/tltest/TLCAgent.scala
+20 −20 src/test/scala/tltest/TLCScalaMessage.scala
2 changes: 1 addition & 1 deletion rocket-chip
Submodule rocket-chip updated 359 files
File renamed without changes.
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