GitHub - jb-gy/verilog-projects: school projects in verilog

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
9.1		9.1
Binary Codes		Binary Codes
Binary Comparators		Binary Comparators
Binary Representations		Binary Representations
Standard Forms		Standard Forms
Verilog Modeling Basic Logic Circuits		Verilog Modeling Basic Logic Circuits
Verilog Transistors		Verilog Transistors
class		class
testbenches 2		testbenches 2
testbenches		testbenches
3BitRegister.v		3BitRegister.v
Adder_Subtractor.v		Adder_Subtractor.v
Arbiter.v		Arbiter.v
Combinational_Logic old.v		Combinational_Logic old.v
Combinational_Practice.v		Combinational_Practice.v
Comparator.v		Comparator.v
Line_Decoder.v		Line_Decoder.v
MUX4to1.v		MUX4to1.v
MooreLab20.v		MooreLab20.v
Moore_machine.v		Moore_machine.v
NAND_Only.v		NAND_Only.v
RippleCarryAdder.v		RippleCarryAdder.v
SSEG_Decoder.v		SSEG_Decoder.v
SevenSegDriver.v		SevenSegDriver.v
asynchronousCounter.v		asynchronousCounter.v
dflipflop.v		dflipflop.v
door_monitor.v		door_monitor.v
pull.txt		pull.txt
test.txt		test.txt