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ExeUnit: add fpWbPort assert
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xiaofeibao-xjtu authored and Tang-Haojin committed May 27, 2024
1 parent 8267453 commit a0998bb
Showing 1 changed file with 20 additions and 0 deletions.
20 changes: 20 additions & 0 deletions src/main/scala/xiangshan/backend/exu/ExeUnit.scala
Original file line number Diff line number Diff line change
Expand Up @@ -142,6 +142,8 @@ class ExeUnitImp(
x => x match {
case IntWB(port, priority) => assert(priority >= 0 && priority <= 2,
s"${exuParams.name}: WbPort must priority=0 or priority=1")
case FpWB(port, priority) => assert(priority >= 0 && priority <= 2,
s"${exuParams.name}: WbPort must priority=0 or priority=1")
case VfWB (port, priority) => assert(priority >= 0 && priority <= 2,
s"${exuParams.name}: WbPort must priority=0 or priority=1")
case _ =>
Expand All @@ -165,6 +167,24 @@ class ExeUnitImp(
)
)
}
val fpWbPort = exuParams.getFpWBPort
if (fpWbPort.isDefined) {
val sameFpPortExuParam = backendParams.allExuParams.filter(_.getFpWBPort.isDefined)
.filter(_.getFpWBPort.get.port == fpWbPort.get.port)
val samePortOneCertainOneUncertain = sameFpPortExuParam.map(_.latencyCertain).contains(true) && sameFpPortExuParam.map(_.latencyCertain).contains(false)
if (samePortOneCertainOneUncertain) sameFpPortExuParam.map(samePort =>
samePort.wbPortConfigs.map(
x => x match {
case FpWB(port, priority) => {
if (!samePort.latencyCertain) assert(priority == sameFpPortExuParam.size - 1,
s"${samePort.name}: FpWbPort $port must latencyCertain priority=0 or latencyUnCertain priority=max(${sameFpPortExuParam.size - 1})")
// Certain latency can be handled by WbBusyTable, so there is no need to limit the exu's WB priority
}
case _ =>
}
)
)
}
val vfWbPort = exuParams.getVfWBPort
if (vfWbPort.isDefined) {
val sameVfPortExuParam = backendParams.allExuParams.filter(_.getVfWBPort.isDefined)
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