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The messages for assertions using hexadecimal numbers will be easier to understand with `g_assert_cmphex`. Cases changed : "cmpuint.*0x", "cmpuint.*<<" Signed-off-by: Inès Varhol <[email protected]> Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Ninad Palsule <[email protected]> Message-ID: <[email protected]> Signed-off-by: Thomas Huth <[email protected]>
Commit e4e98c7 ("pc: q35: Bump max_cpus to 4096 vcpus") increases the supported CPUs for PC Q35 machine. Update maximum CPU numbers for PC Q35 in the document. Signed-off-by: Zhao Liu <[email protected]> Message-ID: <[email protected]> Signed-off-by: Thomas Huth <[email protected]>
tests/vm: update openbsd to release 7.5 Signed-off-by: Brad Smith <[email protected]> Message-ID: <[email protected]> Signed-off-by: Thomas Huth <[email protected]>
This reverts commit c1073e4. The Avocado tests have been removed from Travis a long time ago with commit c5008c7 ("gitlab: add acceptance testing to system builds"), so we don't need to cache the avocado files here anymore. Message-ID: <[email protected]> Signed-off-by: Thomas Huth <[email protected]>
This variable was used to allow jobs to fail without spoiling the overall result. But the required "allow_failures:" hunk has been accidentally removed in commit 9d03f5a ("travis.yml: Remove the "Release tarball" job"), and it was anyway only useful while we still had the x86 jobs here around that were our main CI jobs. Thus let's simply remove this useless variable now. Message-ID: <[email protected]> Signed-off-by: Thomas Huth <[email protected]>
According to our support policy, we'll soon drop our official support
for Ubuntu 20.04 ("Focal Fossa") in QEMU. Thus we should update the
Travis jobs now to a newer release (Ubuntu 22.04 - "Jammy Jellyfish")
for future testing. Since all jobs are using this release now, we
can drop the entries from the individual jobs and use the global
setting again.
Reviewed-by: Daniel P. Berrangé <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
We are doing a lot of cross-compilation tests with GCC in the gitlab-CI already, so we could get some more test coverage by using Clang in the Travis-CI instead. Thus let's switch two additional jobs to use Clang for compilation. Message-ID: <[email protected]> Signed-off-by: Thomas Huth <[email protected]>
Since Ubuntu 22.04 has now been available for more than two years, we can stop actively supporting the previous LTS version of Ubuntu now. Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Message-ID: <[email protected]> Signed-off-by: Thomas Huth <[email protected]>
We need the latest fixes for the lcitool to be able to properly update our CentOS docker file to CentOS Stream 9. Reviewed-by: Daniel P. Berrangé <[email protected]> Message-ID: <[email protected]> Signed-off-by: Thomas Huth <[email protected]>
This update adds the removing of the EXTERNALLY-MANAGED marker files that has been added to the lcitool recently. Quoting Daniel: "For those who don't know, python now commonly blocks the ability to run 'pip install' outside of a venv. This generally makes sense for a precious installation environment. Our containers are disposable though, so a venv has no benefit. Removing the 'EXTERNALLY-MANAGED' allows the historical arbitrary use of 'pip' outside a venv. lcitool just does this unconditionally given the containers are not precious." Reviewed-by: Daniel P. Berrangé <[email protected]> Message-ID: <[email protected]> Signed-off-by: Thomas Huth <[email protected]>
RHEL 9 (and thus also the derivatives) have been available since two years now, so according to QEMU's support policy, we can drop the active support for the previous major version 8 now. Another reason for doing this is that Centos Stream 8 will go EOL soon: https://blog.centos.org/2023/04/end-dates-are-coming-for-centos-stream-8-and-centos-linux-7/ "After May 31, 2024, CentOS Stream 8 will be archived and no further updates will be provided." Thus upgrade our CentOS Stream container to major version 9 now. Reviewed-by: Daniel P. Berrangé <[email protected]> Message-ID: <[email protected]> Signed-off-by: Thomas Huth <[email protected]>
qmp_qom_list_properties can print default values if they are available as qmp_device_list_properties does, because both of them use the ObjectPropertyInfo structure with default_value field. This can be useful when working with "not device" types (e.g. memory-backend). Signed-off-by: Maksim Davydov <[email protected]> Reviewed-by: Vladimir Sementsov-Ogievskiy <[email protected]> Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Markus Armbruster <[email protected]> Message-ID: <[email protected]> Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
To control that creating new machine type doesn't affect the previous types (their compat_props) and to check complex compat_props inheritance we need qmp command to print machine type compatibility properties. This patch adds the ability to get list of all the compat_props of the corresponding supported machines for their comparison via new optional argument of "query-machines" command. Since information on compatibility properties can increase the command output by a factor of 40, add an argument to enable it, default off. Signed-off-by: Maksim Davydov <[email protected]> Reviewed-by: Vladimir Sementsov-Ogievskiy <[email protected]> Acked-by: Markus Armbruster <[email protected]> Message-ID: <[email protected]> Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Add a supportive property to access the path to the QEMU binary Signed-off-by: Maksim Davydov <[email protected]> Reviewed-by: John Snow <[email protected]> Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Message-ID: <[email protected]> Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
This script runs QEMU to obtain compat_props of machines and default
values of different types of drivers to produce comparison table. This
table can be used to compare machine types to choose the most suitable
machine or compare binaries to be sure that migration to the newer version
will save all device properties. Also the json or csv format of this
table can be used to check does a new machine affect the previous ones by
comparing tables with and without the new machine.
Default values (that will be used without machine compat_props) of
properties are needed to fill "holes" in the table (one machine has
the property but another machine not. For instance, 2.12 machine has
`{ "EPYC-" TYPE_X86_CPU, "xlevel", "0x8000000a" }`, but compat_pros of
3.1 machine doesn't have it. Thus, to compare these machines we need to
get unknown value of "EPYC-x86_64-cpu-xlevel" for 3.1 machine. These
unknown values in the table are called "holes". To get values for these
"holes" the script uses list of appropriate methods.)
Notes:
* Some init values from the devices can't be available like properties
from virtio-9p when configure has --disable-virtfs. This situations will
be seen in the table as "unavailable driver".
* Default values can be obtained in an unobvious way, like x86 features.
If the script doesn't know how to get property default value to compare
one machine with another it fills "holes" with "unavailable method". This
is done because script uses whitelist model to get default values of
different types. It means that the method that can't be applied to a new
type that can crash this script. It is better to get an "unavailable
driver" when creating a new machine with new compatible properties than
to break this script. So it turns out a more stable and generic script.
* If the default value can't be obtained because this property doesn't
exist or because this property can't have default value, appropriate
"hole" will be filled by "unknown property" or "no default value"
* If the property is applied to the abstract class, the script collects
default values from all child classes and prints all these classes
* Raw table (--raw flag) should be used with json/csv parameters for
scripts and etc. Human-readable (default) format contains transformed
and simplified values and it doesn't contain lines with the same values
in columns
Example:
./scripts/compare-machine-types.py --mt pc-q35-6.2 pc-q35-7.1
╒══════════════════╤══════════════════════════╤════════════════════════════╤════════════════════════════╕
│ Driver │ Property │ build/qemu-system-x86_64 │ build/qemu-system-x86_64 │
│ │ │ pc-q35-6.2 │ pc-q35-7.1 │
╞══════════════════╪══════════════════════════╪════════════════════════════╪════════════════════════════╡
│ PIIX4_PM │ x-not-migrate-acpi-index │ True │ False │
├──────────────────┼──────────────────────────┼────────────────────────────┼────────────────────────────┤
│ arm-gicv3-common │ force-8-bit-prio │ True │ unavailable driver │
├──────────────────┼──────────────────────────┼────────────────────────────┼────────────────────────────┤
│ nvme-ns │ eui64-default │ True │ False │
├──────────────────┼──────────────────────────┼────────────────────────────┼────────────────────────────┤
│ virtio-mem │ unplugged-inaccessible │ False │ auto │
╘══════════════════╧══════════════════════════╧════════════════════════════╧════════════════════════════╛
Signed-off-by: Maksim Davydov <[email protected]>
Reviewed-by: Vladimir Sementsov-Ogievskiy <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Commit fd3f7d2 ("include/hw/core: Remove i386 conditional on fake_user_interrupt") remove the need to check on NEED_CPU_H. Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Message-Id: <[email protected]>
Move APIC related code split in cpu-sysemu.c and monitor.c to cpu-apic.c. Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Reviewed-by: Zhao Liu <[email protected]> Message-Id: <[email protected]>
FEAT_NMI defines another three new bits in HCRX_EL2: TALLINT, HCRX_VINMI and HCRX_VFNMI. When the feature is enabled, allow these bits to be written in HCRX_EL2. Signed-off-by: Jinjie Ruan <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Reviewed-by: Peter Maydell <[email protected]> Message-id: [email protected] Signed-off-by: Peter Maydell <[email protected]>
When PSTATE.ALLINT is set, an IRQ or FIQ interrupt that is targeted to ELx, with or without superpriority is masked. As Richard suggested, place ALLINT bit in PSTATE in env->pstate. In the pseudocode, AArch64.ExceptionReturn() calls SetPSTATEFromPSR(), which treats PSTATE.ALLINT as one of the bits which are reinstated from SPSR to PSTATE regardless of whether this is an illegal exception return or not. So handle PSTATE.ALLINT the same way as PSTATE.DAIF in the illegal_return exit path of the exception_return helper. With the change, exception entry and return are automatically handled. Signed-off-by: Jinjie Ruan <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Reviewed-by: Peter Maydell <[email protected]> Message-id: [email protected] Signed-off-by: Peter Maydell <[email protected]>
Add support for FEAT_NMI. NMI (FEAT_NMI) is an mandatory feature in ARMv8.8-A and ARM v9.3-A. Signed-off-by: Jinjie Ruan <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Reviewed-by: Peter Maydell <[email protected]> Message-id: [email protected] Signed-off-by: Peter Maydell <[email protected]>
Add ALLINT MSR (immediate) to decodetree, in which the CRm is 0b000x. The EL0 check is necessary to ALLINT, and the EL1 check is necessary when imm == 1. So implement it inline for EL2/3, or EL1 with imm==0. Avoid the unconditional write to pc and use raise_exception_ra to unwind. Signed-off-by: Jinjie Ruan <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Reviewed-by: Peter Maydell <[email protected]> Message-id: [email protected] Signed-off-by: Peter Maydell <[email protected]>
Support ALLINT msr access as follow: mrs <xt>, ALLINT // read allint msr ALLINT, <xt> // write allint with imm Signed-off-by: Jinjie Ruan <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Reviewed-by: Peter Maydell <[email protected]> Message-id: [email protected] Signed-off-by: Peter Maydell <[email protected]>
This only implements the external delivery method via the GICv3. Signed-off-by: Jinjie Ruan <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Reviewed-by: Peter Maydell <[email protected]> Message-id: [email protected] Signed-off-by: Peter Maydell <[email protected]>
According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt with superpriority is always IRQ, never FIQ, so handle NMI same as IRQ in arm_phys_excp_target_el(). Signed-off-by: Jinjie Ruan <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Reviewed-by: Peter Maydell <[email protected]> Message-id: [email protected] Signed-off-by: Peter Maydell <[email protected]>
Add IS and FS bit in ISR_EL1 and handle the read. With CPU_INTERRUPT_NMI or CPU_INTERRUPT_VINMI, both CPSR_I and ISR_IS must be set. With CPU_INTERRUPT_VFNMI, both CPSR_F and ISR_FS must be set. Signed-off-by: Jinjie Ruan <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Reviewed-by: Peter Maydell <[email protected]> Message-id: [email protected] Signed-off-by: Peter Maydell <[email protected]>
Set or clear PSTATE.ALLINT on taking an exception to ELx according to the SCTLR_ELx.SPINTMASK bit. Signed-off-by: Jinjie Ruan <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Reviewed-by: Peter Maydell <[email protected]> Message-id: [email protected] Signed-off-by: Peter Maydell <[email protected]>
Augment the GICv3's QOM device interface by adding one new set of sysbus IRQ line, to signal NMI to each CPU. Signed-off-by: Jinjie Ruan <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Reviewed-by: Peter Maydell <[email protected]> Message-id: [email protected] Signed-off-by: Peter Maydell <[email protected]>
Wire the new NMI and VINMI interrupt line from the GIC to each CPU if it is not GICv2. Signed-off-by: Jinjie Ruan <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Message-id: [email protected] Signed-off-by: Peter Maydell <[email protected]>
According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt with superpriority is always IRQ, never FIQ, so the NMI exception trap entry behave like IRQ. And VINMI(vIRQ with Superpriority) can be raised from the GIC or come from the hcrx_el2.HCRX_VINMI bit, VFNMI(vFIQ with Superpriority) come from the hcrx_el2.HCRX_VFNMI bit. Signed-off-by: Jinjie Ruan <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Reviewed-by: Peter Maydell <[email protected]> Message-id: [email protected] Signed-off-by: Peter Maydell <[email protected]>
Add a property has-nmi to the GICv3 device, and use this to set the NMI bit in the GICD_TYPER register. This isn't visible to guests yet because the property defaults to false and we won't set it in the board code until we've landed all of the changes needed to implement FEAT_GICV3_NMI. Signed-off-by: Jinjie Ruan <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Reviewed-by: Peter Maydell <[email protected]> Message-id: [email protected] Signed-off-by: Peter Maydell <[email protected]>
When mechanically moving the @dirty field to AccelCPUState in commit 79f1926, we neglected cpu->accel is still NULL when we want to dereference it. Reported-by: Volker Rümelin <[email protected]> Suggested-by: Volker Rümelin <[email protected]> Fixes: 79f1926 ("accel/nvmm: Use accel-specific per-vcpu @dirty field") Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Message-Id: <[email protected]>
When mechanically moving the @dirty field to AccelCPUState in commit 9ad4953, we neglected cpu->accel is still NULL when we want to dereference it. Fixes: 9ad4953 ("accel/whpx: Use accel-specific per-vcpu @dirty field") Reported-by: Volker Rümelin <[email protected]> Suggested-by: Volker Rümelin <[email protected]> Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Message-Id: <[email protected]>
The SSE4.1 variant is virtually identical to the SSE2 variant, except for using 'PTEST+JNZ' in place of 'PCMPEQB+PMOVMSKB+CMP+JNE' for testing if an SSE register is all zeroes. The PTEST instruction decodes to two uops, so it can be handled only by the complex decoder, and since CMP+JNE are macro-fused, both sequences decode to three uops. The uops comprising the PTEST instruction dispatch to p0 and p5 on Intel CPUs, so PCMPEQB+PMOVMSKB is comparatively more flexible from dispatch standpoint. Hence, the use of PTEST brings no benefit from throughput standpoint. Its latency is not important, since it feeds only a conditional jump, which terminates the dependency chain. I never observed PTEST variants to be faster on real hardware. Signed-off-by: Alexander Monakov <[email protected]> Signed-off-by: Mikhail Romanov <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Message-Id: <[email protected]>
Thanks to early checks in the inline buffer_is_zero wrapper, the SIMD routines are invoked much more rarely in normal use when most buffers are non-zero. This makes use of AVX512 unprofitable, as it incurs extra frequency and voltage transition periods during which the CPU operates at reduced performance, as described in https://travisdowns.github.io/blog/2020/01/17/avxfreq1.html Signed-off-by: Mikhail Romanov <[email protected]> Signed-off-by: Alexander Monakov <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Message-Id: <[email protected]> Signed-off-by: Richard Henderson <[email protected]>
Test for length >= 256 inline, where is is often a constant. Before calling into the accelerated routine, sample three bytes from the buffer, which handles most non-zero buffers. Signed-off-by: Alexander Monakov <[email protected]> Signed-off-by: Mikhail Romanov <[email protected]> Message-Id: <[email protected]> [rth: Use __builtin_constant_p; move the indirect call out of line.] Signed-off-by: Richard Henderson <[email protected]>
Use of prefetching in bufferiszero.c is quite questionable: - prefetches are issued just a few CPU cycles before the corresponding line would be hit by demand loads; - they are done for simple access patterns, i.e. where hardware prefetchers can perform better; - they compete for load ports in loops that should be limited by load port throughput rather than ALU throughput. Signed-off-by: Alexander Monakov <[email protected]> Signed-off-by: Mikhail Romanov <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Message-Id: <[email protected]>
Increase unroll factor in SIMD loops from 4x to 8x in order to move their bottlenecks from ALU port contention to load issue rate (two loads per cycle on popular x86 implementations). Avoid using out-of-bounds pointers in loop boundary conditions. Follow SSE2 implementation strategy in the AVX2 variant. Avoid use of PTEST, which is not profitable there (like in the removed SSE4 variant). Signed-off-by: Alexander Monakov <[email protected]> Signed-off-by: Mikhail Romanov <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Message-Id: <[email protected]>
Split less-than and greater-than 256 cases. Use unaligned accesses for head and tail. Avoid using out-of-bounds pointers in loop boundary conditions. Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Signed-off-by: Richard Henderson <[email protected]>
Because the three alternatives are monotonic, we don't need to keep a couple of bitmasks, just identify the strongest alternative at startup. Generalize test_buffer_is_zero_next_accel and init_accel by always defining an accel_table array. Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Signed-off-by: Richard Henderson <[email protected]>
Because non-embedded aarch64 is expected to have AdvSIMD enabled, merely double-check with the compiler flags for __ARM_NEON and don't bother with a runtime check. Otherwise, model the loop after the x86 SSE2 function. Use UMAXV for the vector reduction. This is 3 cycles on cortex-a76 and 2 cycles on neoverse-n1. Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Signed-off-by: Richard Henderson <[email protected]>
Benchmark each acceleration function vs an aligned buffer of zeros. Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Signed-off-by: Richard Henderson <[email protected]>
…o staging util/bufferiszero: - Remove sse4.1 and avx512 variants - Reorganize for early test for acceleration - Remove useless prefetches - Optimize sse2, avx2 and integer variants - Add simd acceleration for aarch64 - Add bufferiszero-bench # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmY0/qMdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV+ULQf/T2JSdvG6/EjDCf4N # cnSGiUV2MIeByw8tkrc/fWCNdlulHhk9gbg9l+f2muwK8H/k2BdynbrQnt1Ymmtk # xzM6+PNOcByaovSAkvNweZVbrQX36Yih9S7f3n+xcxfVuvvYhKSLHXLkeqO96LMd # rN+WRpxhReaU3n8/FO7o3S26SRpk7X9kRfShaT7U7ytHGjGsXUvMKIRs30hbsJTB # yjed0a0u54FoSlN6AEqjWdgzaWP8nT65+8Yxe3dzB9hx09UiolZo60eHqYy7Mkno # N6aMOB6gUUbCiKZ3Qk+1zEX97vl26NH3zt5tIIJTWDoIkC3f9qbg1x5hwWLQ3rra # rM8h8w== # =DnZO # -----END PGP SIGNATURE----- # gpg: Signature made Fri 03 May 2024 08:11:31 AM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "[email protected]" # gpg: Good signature from "Richard Henderson <[email protected]>" [ultimate] * tag 'pull-misc-20240503' of https://gitlab.com/rth7680/qemu: tests/bench: Add bufferiszero-bench util/bufferiszero: Add simd acceleration for aarch64 util/bufferiszero: Simplify test_buffer_is_zero_next_accel util/bufferiszero: Introduce biz_accel_fn typedef util/bufferiszero: Improve scalar variant util/bufferiszero: Optimize SSE2 and AVX2 variants util/bufferiszero: Remove useless prefetches util/bufferiszero: Reorganize for early test for acceleration util/bufferiszero: Remove AVX512 variant util/bufferiszero: Remove SSE4.1 variant Signed-off-by: Richard Henderson <[email protected]>
Commit 1ad2134 ("Hardware convenience library") extracted "cpu-common.h" from "cpu-all.h", which uses the LGPL-2.1+ license. Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Message-Id: <[email protected]>
Keep all user emulation headers under the same user/ directory. Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Message-Id: <[email protected]>
Keep all user emulation headers under the same user/ directory. Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Message-Id: <[email protected]>
All user emulation headers are now under include/user/. Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Message-Id: <[email protected]>
"exec/ram_addr.h" shouldn't be used with user emulation. Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Acked-by: Richard Henderson <[email protected]> Message-Id: <[email protected]>
"plugin_mask" was renamed as "event_mask" in commit c006147 ("plugins: create CPUPluginState and migrate plugin_mask"). Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Message-Id: <[email protected]>
Signed-off-by: Anthony PERARD <[email protected]> Acked-by: Paul Durrant <[email protected]> Acked-by: Stefano Stabellini <[email protected]> Message-ID: <[email protected]> Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
The documentation says: ADDV Rm, Rn Rn + Rm -> Rn, overflow -> T But QEMU implementation was: ADDV Rm, Rn Rn + Rm -> Rm, overflow -> T Fix by filling the correct Rm register. Add tests provided by Paul Cercueil. Cc: [email protected] Fixes: ad8d25a ("target-sh4: implement addv and subv using TCG") Reported-by: Paul Cercueil <[email protected]> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2317 Reviewed-by: Richard Henderson <[email protected]> Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Yoshinori Sato <[email protected]> Message-Id: <[email protected]>
The documentation says: SUBV Rm, Rn Rn - Rm -> Rn, underflow -> T The overflow / underflow can be calculated as: T = ((Rn ^ Rm) & (Result ^ Rn)) >> 31 However we were using the incorrect: T = ((Rn ^ Rm) & (Result ^ Rm)) >> 31 Fix by using the Rn register instead of Rm. Add tests provided by Paul Cercueil. Cc: [email protected] Fixes: ad8d25a ("target-sh4: implement addv and subv using TCG") Reported-by: Paul Cercueil <[email protected]> Suggested-by: Paul Cercueil <[email protected]> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2318 Reviewed-by: Richard Henderson <[email protected]> Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Yoshinori Sato <[email protected]> Message-Id: <[email protected]>
To easily compare with the SH4 manual, rename: REG(B11_8) -> Rn REG(B7_4) -> Rm t0 -> result Mention how overflow is calculated. Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Richard Henderson <[email protected]> Reviewed-by: Yoshinori Sato <[email protected]> Message-Id: <[email protected]>
To easily compare with the SH4 manual, rename: REG(B11_8) -> Rn REG(B7_4) -> Rm t0 -> result Mention how underflow is calculated. Reviewed-by: Richard Henderson <[email protected]> Signed-off-by: Philippe Mathieu-Daudé <[email protected]> Message-Id: <[email protected]>
We only support the most recent two versions of macOS (currently macOS 13 Ventura and macOS 14 Sonoma), and our ui/cocoa.m code already assumes at least macOS 12 Monterey or better, because it uses NSScreen safeAreaInsets, which is 12.0-or-newer. Remove the ifdefs that were providing backwards compatibility for building on 10.12 and earlier versions. Signed-off-by: Peter Maydell <[email protected]> Reviewed-by: Daniel P. Berrangé <[email protected]> Message-ID: <[email protected]> Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
…nto staging - Fix NULL dereference in NVMM & WHPX init_vcpu() - Move user emulation headers "exec/user" to "user" - Fix SH-4 ADDV / SUBV opcodes - Drop Cocoa compatility on macOS <= 10.12 - Update Anthony PERARD email # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmY1BE4ACgkQ4+MsLN6t # wN73jg//dbdHQU+4oM7BgTduDZn1ulKz5DtNEJawRP6vxIcSQ+Co2Yd+gdLOSXNI # 2BaoiOQ8cyDEHj1Uud3WVB0GsQYvHrqgXcjeHpX6yFFCZNyRvzEXizJPHKCtq+4e # XQFtfTFftlJdaKCLqyDqVnrVNRacFPm7kinrEQbTSmglAhwnyu3GwsokDAYiJTqp # g0n6mX/pWVEMDNY1HrDsk2Q/pyIZFmzhtuRyXRvi/bh8/BnmMCpySG+2463dnu1O # xIGr2w8ldc+mKn2w2k3wYKDnUHz/NhOkE86tL/ZxIgjCzeenZXwXNdzM+cuAmOZX # L9KIu5io6bTevYVwwHhd5/N6MCqVEhoRmsUQfF0CIkIzxXbyF14M89YHXZo3YJAd # n2uoJ7i6hF/4Pt6Uqlg09+vEk7onwrobnTPnbKHEKNWHNOMKXpq1CBxxcVz2qe24 # +CTAAOOhHqaTjODPSexzHZDZYxugCy1XSqps9AFF1HqUcmsPCL/PQ75YGTJJO0oF # 0V1Yvzjhin26AQS9SglIeXnHxYC26Cg2mXnUpVbryWnG888r0XAGpRl+FEuXK7Ln # /dGuCIWTozypSkG9304IlxlYsOoXhL11NZqINW+W/Tor3dMRQhWUQcHqv98Jl4Ad # rnpzZ0Dhd9ityZdbI0CCMZZZLY5dw1Rq5q407GTJr1CDU4PJBh0= # =N8q0 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 03 May 2024 08:35:42 AM PDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <[email protected]>" [full] * tag 'accel-sh4-ui-20240503' of https://github.com/philmd/qemu: ui/cocoa.m: Drop old macOS-10.12-and-earlier compat ifdefs target/sh4: Rename TCGv variables as manual for SUBV opcode target/sh4: Rename TCGv variables as manual for ADDV opcode target/sh4: Fix SUBV opcode target/sh4: Fix ADDV opcode MAINTAINERS: Update my email address plugins: Update stale comment plugins/api: Only include 'exec/ram_addr.h' with system emulation coverity: Update user emulation regexp user: Move 'thunk.h' from 'exec/user' to 'user' user: Move 'abitypes.h' from 'exec/user' to 'user' exec: Include missing license in 'exec/cpu-common.h' accel/whpx: Fix NULL dereference in whpx_init_vcpu() accel/nvmm: Fix NULL dereference in nvmm_init_vcpu() Signed-off-by: Richard Henderson <[email protected]>
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Merge master with upstream so I can create a fresh branch for 65816 / Apple IIGS work.