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Code refactoring (ferrandi#121)
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Ansaya authored Feb 22, 2023
1 parent a71eaf8 commit 048ca4a
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Showing 24 changed files with 283 additions and 272 deletions.
2 changes: 2 additions & 0 deletions clang-format-all.sh
Original file line number Diff line number Diff line change
Expand Up @@ -28,6 +28,8 @@ fi
# Variable that will hold the name of the clang-format command
FMT="$(find $(echo $PATH | sed 's/:/ /g') -regextype posix-extended -regex '.*/clang-format-[0-9]{2}' | sort --version-sort --field-separator=- --key=2,2 | tail -n1)"

echo "Using $($FMT --version)"

# Check if we found a working clang-format
if [ -z "$FMT" ]; then
echo "failed to find clang-format"
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7 changes: 7 additions & 0 deletions src/EucalyptusParameter.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -63,6 +63,7 @@
#define OPT_ALTERA_ROOT (1 + OPT_MENTOR_OPTIMIZER)
#define OPT_NANOXPLORE_ROOT (1 + OPT_ALTERA_ROOT)
#define OPT_NANOXPLORE_BYPASS (1 + OPT_NANOXPLORE_ROOT)
#define OPT_PARALLEL_BACKEND (1 + OPT_NANOXPLORE_BYPASS)

#include "utility.hpp"
#include "utility/fileIO.hpp"
Expand Down Expand Up @@ -174,6 +175,7 @@ int EucalyptusParameter::Exec()
{"nanoxplore-root", optional_argument, nullptr, OPT_NANOXPLORE_ROOT},
{"nanoxplore-bypass", optional_argument, nullptr, OPT_NANOXPLORE_BYPASS},
{"xilinx-root", optional_argument, nullptr, OPT_XILINX_ROOT},
{"parallel-backend", no_argument, nullptr, OPT_PARALLEL_BACKEND},
{nullptr, 0, nullptr, 0}
};

Expand Down Expand Up @@ -245,6 +247,11 @@ int EucalyptusParameter::Exec()
setOption(OPT_xilinx_root, GetPath(optarg));
break;
}
case OPT_PARALLEL_BACKEND:
{
setOption(OPT_parallel_backend, true);
break;
}
/// output options
case 'w':
{
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5 changes: 2 additions & 3 deletions src/HLS/interface/WB4/WB4Intercon_interface.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -46,7 +46,6 @@
#include "hls_manager.hpp"
#include "hls_target.hpp"
#include "memory.hpp"
#include "memory_symbol.hpp"
#include "structural_manager.hpp"
#include "structural_objects.hpp"
#include "technology_manager.hpp"
Expand Down Expand Up @@ -109,7 +108,7 @@ static unsigned long long get_data_bus_bitsize(const hlsRef HLS, const HLS_manag
{
const auto function_behavior = HLSMgr->CGetFunctionBehavior(HLS->functionId);
const auto behavioral_helper = function_behavior->CGetBehavioralHelper();
std::map<unsigned int, memory_symbolRef> parameters = HLSMgr->Rmem->get_function_parameters(HLS->functionId);
const auto parameters = HLSMgr->Rmem->get_function_parameters(HLS->functionId);

auto data_bus_bitsize = HLSMgr->Rmem->get_bus_data_bitsize();
for(const auto& function_parameter : parameters)
Expand Down Expand Up @@ -263,7 +262,7 @@ static void buildCircuit(structural_managerRef SM, structural_objectRef wrappedO
masters.push_back(wrappedObj);
}

const CustomOrderedSet<unsigned int> additionalTops = HLSMgr->CGetCallGraphManager()->GetAddressedFunctions();
const auto additionalTops = HLSMgr->CGetCallGraphManager()->GetAddressedFunctions();
for(unsigned int itr : additionalTops)
{
std::string functionName = tree_helper::name_function(TM, itr);
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14 changes: 7 additions & 7 deletions src/HLS/interface/minimal/minimal_interface.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -155,8 +155,8 @@ void minimal_interface::build_wrapper(structural_objectRef wrappedObj, structura
std::map<unsigned long long, structural_objectRef> null_values;

const auto& base_address = HLSMgr->base_address;
const auto Has_extern_allocated_data = HLSMgr->Rmem->get_memory_address() - base_address > 0;
const auto Has_unknown_addresses = HLSMgr->Rmem->has_unknown_addresses();
const auto has_extern_mem = HLSMgr->Rmem->get_memory_address() - base_address > 0;
const auto has_unknown_addresses = HLSMgr->Rmem->has_unknown_addresses();
const auto FB = HLSMgr->CGetFunctionBehavior(funId);
const auto channels_number = FB->GetChannelsNumber();
const auto channels_type = FB->GetChannelsType();
Expand Down Expand Up @@ -353,7 +353,7 @@ void minimal_interface::build_wrapper(structural_objectRef wrappedObj, structura
};
if(!Has_intern_shared_data)
{
if(!Has_extern_allocated_data)
if(!has_extern_mem)
{
if(!with_master && with_slave)
{
Expand All @@ -372,7 +372,7 @@ void minimal_interface::build_wrapper(structural_objectRef wrappedObj, structura
/// do nothing
/// it may happen with ALL_BRAM memory allocation policy
}
else if(with_master && with_slave && Has_unknown_addresses &&
else if(with_master && with_slave && has_unknown_addresses &&
HLSMgr->Rmem->get_allocated_internal_memory() == 0)
{
/// intern data is not externally visible
Expand All @@ -386,7 +386,7 @@ void minimal_interface::build_wrapper(structural_objectRef wrappedObj, structura
portsToSkip.insert(wrappedObj->find_member("Sout_Rdata_ram", port_o_K, wrappedObj));
portsToSkip.insert(wrappedObj->find_member("Sout_DataRdy", port_o_K, wrappedObj));
}
else if(with_master && with_slave && !Has_unknown_addresses)
else if(with_master && with_slave && !has_unknown_addresses)
{
/// slave INs connections
portsToConnect[wrappedObj->find_member("S_oe_ram", port_o_K, wrappedObj)] =
Expand Down Expand Up @@ -426,7 +426,7 @@ void minimal_interface::build_wrapper(structural_objectRef wrappedObj, structura
}
else
{
if(with_master && !Has_unknown_addresses && HLSMgr->Rmem->get_ext_memory_variables().empty())
if(with_master && !has_unknown_addresses && HLSMgr->Rmem->get_ext_memory_variables().empty())
{
THROW_ASSERT(channels_type != (MemoryAllocation_ChannelsType::MEM_ACC_P1N), "unexpected condition");
/// allocate the unique shared memory
Expand Down Expand Up @@ -486,7 +486,7 @@ void minimal_interface::build_wrapper(structural_objectRef wrappedObj, structura
shared_memory_module->SetParameter("n_elements", STR(vec_size));
shared_memory_module->SetParameter("data_size", STR(bus_data_bitsize));
shared_memory_module->SetParameter("BRAM_BITSIZE", STR(bram_bitsize));
if((Has_extern_allocated_data) || Has_unknown_addresses)
if(has_extern_mem || has_unknown_addresses)
{
shared_memory_module->SetParameter("BUS_PIPELINED", "0");
}
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86 changes: 51 additions & 35 deletions src/HLS/module_generator/OpenModuleGenerator.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -55,14 +55,15 @@ OpenModuleGenerator::OpenModuleGenerator(const HLS_managerRef& _HLSMgr) : Regist

void OpenModuleGenerator::InternalExec(std::ostream& out, const module* /* mod */, unsigned int /* function_id */,
vertex /* op_v */, const HDLWriter_Language /* language */,
const std::vector<ModuleGenerator::parameter>& _p,
const std::vector<ModuleGenerator::parameter>& /* _p */,
const std::vector<ModuleGenerator::parameter>& /* _ports_in */,
const std::vector<ModuleGenerator::parameter>& /* _ports_out */,
const std::vector<ModuleGenerator::parameter>& /* _ports_inout */)
{
out << " // verilator lint_off LITENDIAN\n";
out << "parameter MAX_BUFF_SIZE = 256;\n";
out << "reg [0:8*MAX_BUFF_SIZE-1] buffer_name;\n";
out << "reg [0:8*MAX_BUFF_SIZE-1] buffer_name_old;\n";
out << "\n";
out << " `ifndef _SIM_HAVE_CLOG2\n";
out << " function integer log2;\n";
Expand All @@ -82,12 +83,6 @@ void OpenModuleGenerator::InternalExec(std::ostream& out, const module* /* mod *
out << " parameter nbits_buffer = log2(MAX_BUFF_SIZE);\n";
out << " `endif\n";

std::string sensitivity;
for(auto i = 0U; i < _p.size(); i++)
{
sensitivity += " or " + _p[i].name;
}

std::string modes = "in2";

std::string flags_string = "(" + modes + " & " + STR(O_RDWR) + ") != 0 && (" + modes + " & " + STR(O_APPEND) +
Expand All @@ -108,14 +103,16 @@ void OpenModuleGenerator::InternalExec(std::ostream& out, const module* /* mod *
" reg [BITSIZE_Mout_Wdata_ram-1:0] Mout_Wdata_ram;\n"
" reg [BITSIZE_Mout_data_ram_size-1:0] Mout_data_ram_size;\n"
" reg active_request;\n"
" reg active_request_now;\n"
" reg active_request_next;\n"
" reg M_DataRdy_reg;\n"
" reg [BITSIZE_M_Rdata_ram-1:0]M_Rdata_ram_reg;\n"
" \n"
" parameter [1:0] S_0 = 2'd0,\n"
" S_1 = 2'd1,\n"
" S_2 = 2'd2,\n"
" S_3 = 2'd3;\n"
" reg [3:0] _present_state 1INIT_ZERO_VALUE;\n"
" reg [3:0] _next_state;\n"
" S_2 = 2'd2;\n"
" reg [1:0] _present_state 1INIT_ZERO_VALUE;\n"
" reg [1:0] _next_state;\n"
" reg [63:0] data1;\n"
" reg [7:0] data1_size;\n"
" \n"
Expand All @@ -131,35 +128,55 @@ void OpenModuleGenerator::InternalExec(std::ostream& out, const module* /* mod *
" active_request <= active_request_next;\n"
" end\n"
" end\n"
" assign out1 = {1'b0,temp_out1[30:0]};\n"
" always @(posedge clock 1RESET_EDGE)\n"
" begin\n"
" if (1RESET_VALUE)\n"
" begin\n"
" active_request <= 0;\n"
" end\n"
" else\n"
" begin\n"
" active_request <= active_request_next;\n"
" end\n"
" end\n"
" always @(posedge clock 1RESET_EDGE)\n"
" if (1RESET_VALUE)\n"
" begin\n"
" _present_state <= S_0;\n"
" _present_pointer <= {BITSIZE_Mout_addr_ram{1'b0}};\n"
" _present_index <= {nbits_buffer{1'b0}};\n"
" buffer_name_old <= {8*MAX_BUFF_SIZE{1'b0}};\n"
" M_DataRdy_reg <= 0;\n"
" M_Rdata_ram_reg <= 0;\n"
" end\n"
" else\n"
" begin\n"
" _present_state <= _next_state;\n"
" _present_pointer <= _next_pointer;\n"
" _present_index <= _next_index;\n"
" buffer_name_old <= buffer_name;\n"
" M_DataRdy_reg <= M_DataRdy;\n"
" M_Rdata_ram_reg <= M_Rdata_ram;\n"
" end\n"
" \n"
" always @(_present_state or _present_pointer or _present_index or start_port or M_DataRdy or Min_we_ram or "
"Min_oe_ram or Min_Wdata_ram or Min_addr_ram or Min_data_ram_size" +
sensitivity +
" or M_Rdata_ram)\n"
" always @(*)\n"
" begin\n"
" Mout_we_ram = Min_we_ram;\n"
" Mout_Wdata_ram = Min_Wdata_ram;\n"
" Mout_oe_ram = Min_oe_ram;\n"
" Mout_addr_ram = Min_addr_ram;\n"
" Mout_data_ram_size = Min_data_ram_size;\n"
" Mout_oe_ram = Min_oe_ram;\n"
" Mout_addr_ram = Min_addr_ram;\n"
" Mout_data_ram_size = Min_data_ram_size;\n"
" done_port = 1'b0;\n"
" _next_state = _present_state;\n"
" _next_pointer = _present_pointer;\n"
" _next_index = _present_index;\n"
" active_request_next = 1'b0;\n"
" active_request_now = 1'b0;\n"
" buffer_name = buffer_name_old;\n"
" case (_present_state)\n"
" S_0:\n"
" if(start_port)\n"
Expand All @@ -169,23 +186,32 @@ void OpenModuleGenerator::InternalExec(std::ostream& out, const module* /* mod *
" _next_state = S_1; \n"
" active_request_next = 1'b1;\n"
" buffer_name = 0; \n"
" _next_pointer = 0;\n"
" _next_index = {nbits_buffer{1'b0}};\n"
" _next_state = S_1; \n"
" active_request_next = 1'b1;\n"
" buffer_name = 0; \n"
" end\n"
" \n"
" S_1:\n"
" begin\n"
" Mout_addr_ram[BITSIZE_Mout_addr_ram-1:0] = (in1[BITSIZE_Mout_addr_ram-1:0] + _present_pointer) & "
"{BITSIZE_Mout_addr_ram{active_request}};\n"
" Mout_data_ram_size = {{BITSIZE_Mout_data_ram_size-4{1'b0}}, 4'd8} & "
"{BITSIZE_Mout_data_ram_size{active_request}};\n"
" Mout_oe_ram = active_request;\n"
" if(M_DataRdy)\n"
" if(M_DataRdy_reg)\n"
" begin\n"
" buffer_name[_present_index*8 +:8] = M_Rdata_ram[7:0];\n"
" if(M_Rdata_ram[7:0] == 8'd0)\n"
" buffer_name[_present_index*8 +:8] = M_Rdata_ram_reg[7:0];\n"
" if(M_Rdata_ram_reg[7:0] == 8'd0)\n"
" _next_state = S_2;\n"
" else\n"
" _next_state = S_3;\n"
" begin\n"
" _next_state = S_1;\n"
" _next_pointer = _present_pointer+1'd1;\n"
" _next_index = _present_index+1'd1;\n"
" active_request_now = 1'b1;\n"
" end\n"
" end\n"
" Mout_addr_ram[BITSIZE_Mout_addr_ram-1:0] = (in1[BITSIZE_Mout_addr_ram-1:0] + _next_pointer) & "
"{BITSIZE_Mout_addr_ram{active_request || active_request_now}};\n"
" Mout_data_ram_size = {{BITSIZE_Mout_data_ram_size-4{1'b0}}, 4'd8} & "
"{BITSIZE_Mout_data_ram_size{active_request || active_request_now}};\n"
" Mout_oe_ram = active_request || active_request_now;\n"
" end\n"
" S_2:\n"
" begin\n"
Expand All @@ -197,16 +223,6 @@ void OpenModuleGenerator::InternalExec(std::ostream& out, const module* /* mod *
" done_port = 1'b1;\n"
" _next_state = S_0;\n"
" end\n"
" S_3:\n"
" begin\n"
" if(!M_DataRdy)\n"
" begin\n"
" _next_pointer = _present_pointer+1'd1;\n"
" _next_index = _present_index+1'd1;\n"
" _next_state = S_1;\n"
" active_request_next = 1'b1;\n"
" end\n"
" end\n"
" endcase\n "
" end\n";

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