Fixed cycle computation. An offset of 100ns was previously introduced…

… before start begins.

etc/lib/technology/NC_HLS_IPs.xml

@@ -1262,7 +1262,7 @@ always @(negedge clock)
     res_file = $fopen("results.txt","w");
     $display("__builtin_trap called");
     $fwrite(res_file, "0\\t");
-    $fwrite(res_file, "%d\\t", $time);
+    $fwrite(res_file, "%d\\t", $time>=`INIT_TIME?$time-`INIT_TIME:$time);
     $fwrite(res_file, "ns\\n");
     $fclose(res_file);
     $finish;
@@ -1312,7 +1312,7 @@ always @(negedge clock)
     res_file = $fopen("results.txt","w");
     $display("__builtin_unreachable called");
     $fwrite(res_file, "0\\t");
-    $fwrite(res_file, "%d\\t", $time);
+    $fwrite(res_file, "%d\\t", $time>=`INIT_TIME?$time-`INIT_TIME:$time);
     $fwrite(res_file, "ns\\n");
     $fclose(res_file);
     $finish;
@@ -1388,7 +1388,7 @@ always @(negedge clock)
     res_file = $fopen("results.txt","w");
     $display("Exit called");
     $fwrite(res_file, "%d\\t", (status!=0 ? 0 : 1));
-    $fwrite(res_file, "%d\\t", $time);
+    $fwrite(res_file, "%d\\t", $time>=`INIT_TIME?$time-`INIT_TIME:$time);
     $fwrite(res_file, "ns\\n");
     $fclose(res_file);
     $finish;
@@ -1464,7 +1464,7 @@ always @(negedge clock)
     res_file = $fopen("results.txt","w");
     $display("Abort called");
     $fwrite(res_file, "0\\t");
-    $fwrite(res_file, "%d\\t", $time);
+    $fwrite(res_file, "%d\\t", $time>=`INIT_TIME?$time-`INIT_TIME:$time);
     $fwrite(res_file, "ns\\n");
     $fclose(res_file);
     $finish;

src/HLS/simulation/testbench_generation_base_step.cpp

@@ -41,69 +41,42 @@
  * @author Pietro Fezzardi <[email protected]>
  *
  */
-/// Autoheader include
+#include "testbench_generation_base_step.hpp"
+
 #include "config_PACKAGE_BUGREPORT.hpp"
 #include "config_PACKAGE_NAME.hpp"
 #include "config_PACKAGE_VERSION.hpp"
 
-/// Header include
-#include "testbench_generation_base_step.hpp"
-
-#include <utility>
-
-///. include
+#include "HDL_manager.hpp"
 #include "Parameter.hpp"
-
-/// behavior include
+#include "SimulationInformation.hpp"
+#include "behavioral_helper.hpp"
 #include "call_graph_manager.hpp"
-
-/// circuit include
-#include "structural_manager.hpp"
-#include "structural_objects.hpp"
-
-/// constants include
-#include "testbench_generation_constants.hpp"
-
-/// design_flows include
 #include "design_flow_manager.hpp"
-
-/// design_flows/backend/ToHDL includes
-#include "HDL_manager.hpp"
-#include "language_writer.hpp"
-
-/// HLS include
+#include "fu_binding.hpp"
 #include "hls.hpp"
 #include "hls_constraints.hpp"
 #include "hls_manager.hpp"
 #include "hls_target.hpp"
-
-/// HLS/binding/module include
-#include "fu_binding.hpp"
-
-/// HLS/memory include
+#include "language_writer.hpp"
+#include "math_function.hpp"
 #include "memory.hpp"
-
-// include from HLS/simulation
-#include "SimulationInformation.hpp"
-
-#if HAVE_FROM_DISCREPANCY_BUILT
-// include from HLS/vcd
-#include "Discrepancy.hpp"
-#endif
-
-/// technology/physical_library
+#include "structural_manager.hpp"
+#include "structural_objects.hpp"
 #include "technology_wishbone.hpp"
-
-/// tree include
-#include "behavioral_helper.hpp"
+#include "testbench_generation_constants.hpp"
 #include "tree_helper.hpp"
 #include "tree_manager.hpp"
 #include "tree_node.hpp"
 #include "tree_reindex.hpp"
 
-/// utility include
-#include "fileIO.hpp"
-#include "math_function.hpp"
+#if HAVE_FROM_DISCREPANCY_BUILT
+#include "Discrepancy.hpp"
+#endif
+
+#include <boost/filesystem/operations.hpp>
+#include <boost/filesystem/path.hpp>
+#include <utility>
 
 TestbenchGenerationBaseStep::TestbenchGenerationBaseStep(const ParameterConstRef _parameters,
                                                          const HLS_managerRef _HLSMgr,
@@ -1974,7 +1947,8 @@ void TestbenchGenerationBaseStep::write_hdl_testbench_prolog() const
    writer->write_comment("CONSTANTS DECLARATION\n");
    writer->write(
        "`define EOF 32'hFFFF_FFFF\n`define NULL 0\n`define MAX_COMMENT_LENGTH 1000\n`define SIMULATION_LENGTH " +
-       STR(parameters->getOption<long long int>(OPT_max_sim_cycles)) + "\n\n");
+       STR(parameters->getOption<long long int>(OPT_max_sim_cycles)) + "\n`define INIT_TIME  " +
+       std::string(STR_CST_INIT_TIME) + "\n\n");
    auto half_target_period_string = STR(target_period / 2);
    // If the value it is integer, we add .0 to describe a float otherwise modelsim returns conversion error
    if(half_target_period_string.find('.') == std::string::npos)
@@ -2433,7 +2407,7 @@ void TestbenchGenerationBaseStep::testbench_controller_machine() const
    writer->write("            __next_state = 2;\n");
    writer->write("         end\n");
    writer->write("       2:\n");
-   writer->write("         if(currTime > 100)\n");
+   writer->write("         if(currTime > `INIT_TIME)\n");
    writer->write("           begin\n");
    writer->write("              next_start_port = 1;\n");
    writer->write("              if (done_port == 1'b1)\n");
@@ -2732,7 +2706,8 @@ void TestbenchGenerationBaseStep::write_max_simulation_time_control() const
    writer->write(STR(STD_OPENING_CHAR));
    writer->write("begin\n");
    writer->write("currTime = $time;\n");
-   writer->write("if (($time - startTime)/`CLOCK_PERIOD > `SIMULATION_LENGTH)\n");
+   writer->write("if ($time >= startTime && (($time - startTime)/`CLOCK_PERIOD > "
+                 "`SIMULATION_LENGTH))\n");
    writer->write(STR(STD_OPENING_CHAR));
    writer->write("begin\n");
    writer->write("$display(\"Simulation not completed into %d cycles\", `SIMULATION_LENGTH);\n");

src/constants/testbench_generation_constants.hpp

@@ -46,4 +46,7 @@
 /// threshold used to switch from data directly printed to data written to a file and then copied
 #define DATA_SIZE_THRESHOLD (1024 * 8)
 
+/// Constant delay for testbench initialization. It is relevant for XILINX devices.
+#define STR_CST_INIT_TIME "100"
+
 #endif

src/design_flows/backend/ToHDL/writer/verilog_writer.cpp

@@ -41,22 +41,23 @@
  * Last modified by $Author$
  *
  */
+#include "verilog_writer.hpp"
 
-/// Autoheader include
 #include "config_HAVE_FROM_C_BUILT.hpp"
 
-#include "verilog_writer.hpp"
-
 #include "HDL_manager.hpp"
-
-#include "technology_manager.hpp"
-#include "time_model.hpp"
-
 #include "NP_functionality.hpp"
+#include "Parameter.hpp"
 #include "dbgPrintHelper.hpp"
 #include "exceptions.hpp"
+#include "indented_output_stream.hpp"
+#include "state_transition_graph_manager.hpp"
+#include "string_manipulation.hpp"
 #include "structural_objects.hpp"
-#include "tree_helper.hpp"
+#include "technology_manager.hpp"
+#include "technology_node.hpp"
+#include "testbench_generation_constants.hpp"
+#include "time_model.hpp"
 
 #include <algorithm>
 #include <boost/algorithm/string.hpp>
@@ -65,25 +66,9 @@
 #include <fstream>
 #include <functional>
 #include <iosfwd>
-
-#include "state_transition_graph_manager.hpp"
-
-///. include
-#include "Parameter.hpp"
-
-/// STD include
 #include <limits>
-
-/// STL include
 #include <utility>
 
-/// technology include
-#include "technology_node.hpp"
-
-/// utility include
-#include "indented_output_stream.hpp"
-#include "string_manipulation.hpp" // for GET_CLASS
-
 #define VERILOG_2001_SUPPORTED
 
 const std::map<std::string, std::string> verilog_writer::builtin_to_verilog_keyword = {
@@ -2325,6 +2310,7 @@ void verilog_writer::write_timing_specification(const technology_managerConstRef
 
 void verilog_writer::write_header()
 {
+   indented_output_stream->Append("`define INIT_TIME " + std::string(STR_CST_INIT_TIME) + "\n");
    indented_output_stream->Append("`ifdef __ICARUS__\n");
    indented_output_stream->Append("  `define _SIM_HAVE_CLOG2\n");
    indented_output_stream->Append("`endif\n");

src/design_flows/design_flows.am

@@ -160,6 +160,7 @@ if BUILD_LIB_TO_HDL
    -I$(top_srcdir)/src \
    -I$(top_srcdir)/src/behavior \
    -I$(top_srcdir)/src/circuit \
+   -I$(top_srcdir)/src/constants/ \
    -I$(top_srcdir)/src/design_flows \
    -I$(top_srcdir)/src/design_flows/backend/ToHDL \
    -I$(top_srcdir)/src/graph \