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Free trading strategies for Freqtrade bot

Python 3,894 1,205 Updated Jan 20, 2025

A JavaScript / TypeScript / Python / C# / PHP / Go cryptocurrency trading API with support for more than 100 bitcoin/altcoin exchanges

Python 35,031 7,763 Updated Mar 12, 2025

🤖 Open-source crypto trading bot | 📈 DCA & GRID strategies | ✨ UI | ⭐ Star to support the project!

TypeScript 956 82 Updated Mar 6, 2025

Examples and guides for using the OpenAI API

MDX 62,220 10,043 Updated Mar 12, 2025

Free, open source crypto trading bot

Python 37,179 7,315 Updated Mar 11, 2025

Python Backtesting library for trading strategies

Python 16,318 4,221 Updated Aug 19, 2024

This tool translates synthesizable SystemC code to synthesizable SystemVerilog.

C++ 266 40 Updated Feb 28, 2025

A graphical processor simulator and assembly editor for the RISC-V ISA

C++ 2,736 283 Updated Mar 2, 2025

DRAMSys a SystemC TLM-2.0 based DRAM simulator.

C++ 244 60 Updated Oct 31, 2024

Pseudo API for Google Trends

Python 3,402 833 Updated Aug 10, 2024

Technical Analysis Library using Pandas and Numpy

Jupyter Notebook 4,540 1,050 Updated Jul 17, 2024

lowRISC Style Guides

397 122 Updated Sep 13, 2024

OpenTitan: Open source silicon root of trust

SystemVerilog 2,721 820 Updated Mar 12, 2025

A dependency management tool for hardware projects.

Rust 283 42 Updated Jan 31, 2025

Common SystemVerilog components

SystemVerilog 584 156 Updated Feb 28, 2025

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

SystemVerilog 1,234 278 Updated Feb 27, 2025

A SystemC productivity library: https://minres.github.io/SystemC-Components/

JavaScript 102 28 Updated Feb 25, 2025

A Happy and lightweight Python Package that Provides an API to search for articles on Google News and returns a JSON response.

Python 794 112 Updated Mar 5, 2025

RISC-V SystemC-TLM simulator

C 297 74 Updated Dec 18, 2024
C++ 7 1 Updated Jan 30, 2021

SystemC training aimed at TLM.

C++ 28 9 Updated Jul 31, 2020

BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/

Tcl 83 12 Updated Jan 5, 2025

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

SystemVerilog 276 60 Updated Nov 25, 2019

contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols

C++ 56 11 Updated Feb 21, 2025

SystemC/TLM-2.0 Co-simulation framework

Verilog 236 70 Updated Oct 25, 2024

A modeling library with virtual components for SystemC and TLM simulators

C++ 145 37 Updated Mar 11, 2025

Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM stan…

C++ 299 66 Updated Dec 11, 2024

Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM stan…

C++ 2 Updated Feb 16, 2024

Topics in Machine Learning Accelerator Design

68 17 Updated Feb 16, 2023
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