for generate

.gitignore

@@ -363,3 +363,5 @@ sim
 
 !ready-to-run/*
 
+novas*
+verdiLog/

src/main/scala/xiangshan/backend/CtrlBlock.scala

@@ -26,6 +26,7 @@ import xiangshan._
 import xiangshan.ExceptionNO._
 import xiangshan.mem.mdp.{LFST, SSIT, WaitTable}
 import xiangshan.mem.LsqEnqIO
+import xiangshan.mem._
 import xiangshan.vector._
 import xiangshan.vector.SIRenameInfo
 import xiangshan.vector.vtyperename._
@@ -40,7 +41,6 @@ import xiangshan.backend.rob.{Rob, RobCSRIO, RobLsqIO, RobPtr}
 import xiangshan.backend.issue.DqDispatchNode
 import xiangshan.backend.execute.fu.FuOutput
 import xiangshan.backend.execute.fu.csr.vcsr.VCSRWithVtypeRenameIO
-import xiangshan.mem._
 import xiangshan.backend.execute.fu.csr.vcsr.VCSRWithRobIO
 
 class CtrlToFtqIO(implicit p: Parameters) extends XSBundle {

src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala

@@ -145,7 +145,7 @@ class DispatchQueue (size: Int, enqNum: Int, deqNum: Int)(implicit p: Parameters
     when(io.enq.canAccept){assert(Mux(i.U < actualEnqNum, squeezedEnqs(i).valid === true.B, squeezedEnqs(i).valid === false.B))}
   }
   for(i <- 1 until squeezedEnqs.length){
-    when(squeezedEnqs(i).valid){assert(squeezedEnqs(i).bits.robIdx > squeezedEnqs(i - 1).bits.robIdx)}
+    when(squeezedEnqs(i).valid){assert(squeezedEnqs(i).bits.robIdx >= squeezedEnqs(i - 1).bits.robIdx)}
   }
   assert(flushNum <= validEntriesNum)
   private val enqFlushNextMask = UIntToMask((enqPtr - flushNum).value, size)

src/main/scala/xiangshan/backend/execute/exublock/MemBlock.scala

@@ -224,7 +224,7 @@ class MemBlockImp(outer: MemBlock) extends BasicExuBlockImp(outer)
     require(wb.out.length == 1)
     wb.out.head._1
   })
-  private val vstuWritebacks = outer.stuWritebackNodes.map(wb => {
+  private val vstuWritebacks = outer.vstuWritebackNodes.map(wb => {
     require(wb.out.length == 1)
     wb.out.head._1
   })

src/main/scala/xiangshan/backend/execute/fu/csr/vcsr/VCSR.scala

@@ -122,12 +122,15 @@ class VCSR(implicit p: Parameters) extends FUWithRedirect with HasVCSRConst {
 
     val avl = Mux(isVsetivli, Cat(0.U(59.W), imm(4, 0)), src0)
     val vlNewSetivli = Mux(vlmax >= avl, avl, vlmax)
-    val vlNewOther = Mux(!rs1IsX0, Mux(src0 >= vlmax, vlmax, src0), Mux(!rdIsX0, vlmax, uop.vCsrInfo.vl))
+    val vlNewOther = Mux(!rs1IsX0, Mux(src0 >= vlmax, vlmax, src0), Mux(!rdIsX0, vlmax, src0))
 
     val vill = 0.U(1.W) //TODO: set vill -> illegal vtype set
 
+    vcsr_io.vtype.vtypeWbToRename.bits.uop := io.in.bits.uop
     vcsr_io.vtype.vtypeWbToRename.bits.data := Cat(vill, 0.U(55.W), vtypeValue)
     vcsr_io.vtype.vtypeWbToRename.valid := (isVsetivli || isVsetvl || isVsetvli) && io.in.fire()
+    vcsr_io.vtype.vlRead.readEn := false.B
+    vcsr_io.vtype.vtypeRead.readEn := false.B
 
     // CSRRW
 
@@ -140,6 +143,8 @@ class VCSR(implicit p: Parameters) extends FUWithRedirect with HasVCSRConst {
     )
     val addr = imm(11, 0)
     val rdata = Wire(UInt(XLEN.W))
+    //TODO: fill rdata
+    rdata := 0.U
     val csri = ZeroExt(imm(16, 12), XLEN)
     val wdata = LookupTree(func, List(
         CSROpType.wrt  -> src1,

src/main/scala/xiangshan/backend/issue/IntRs/IntegerReservationStation.scala

@@ -96,7 +96,7 @@ class IntegerReservationStationImpl(outer:IntegerReservationStation, param:RsPar
     wkp.bits.pdest := elm.bits.uop.pdest
     wkp.bits.robPtr := elm.bits.uop.robIdx
     wkp.bits.lpv := 0.U.asTypeOf(wkp.bits.lpv)
-    wkp.bits.destType := Mux(elm.bits.uop.ctrl.rfWen, SrcType.reg, SrcType.default)
+    wkp.bits.destType := Mux(elm.bits.uop.ctrl.rfWen, SrcType.reg, SrcType.DC)
     wkp
   }))
   private val rsWakeupWidth = (wakeupSignals ++ internalAluWakeupSignals ++ internalMulWakeupSignals ++ extraAluWakeupSignals).length

src/main/scala/xiangshan/backend/issue/MemRs/MemoryReservationStation.scala

@@ -212,7 +212,6 @@ class MemoryReservationStationImpl(outer:MemoryReservationStation, param:RsParam
     vectorBusyTableReadIdx = vectorBusyTableReadIdx + 3
     //assert(type0 === SrcType.reg)
     when(source.valid) {
-      assert(type0 === SrcType.reg)
       assert(FuType.memoryTypes.map(_ === source.bits.ctrl.fuType).reduce(_||_))
     }
   })

src/main/scala/xiangshan/backend/issue/WakeupQueue.scala

@@ -53,20 +53,20 @@ object WakeupQueue {
     val res = Wire(Valid(new WakeUpInfo()(p)))
     if(latency > 0) {
       val wakeupQueue = Module(new WakeupQueue(latency)(p))
-      wakeupQueue.io.in.valid := in.fire
+      wakeupQueue.io.in.valid := in.fire && (in.bits.info.fpWen || in.bits.info.rfWen)
       wakeupQueue.io.earlyWakeUpCancel := cancel
       wakeupQueue.io.in.bits.lpv := in.bits.info.lpv
       wakeupQueue.io.in.bits.robPtr := in.bits.info.robPtr
       wakeupQueue.io.in.bits.pdest := in.bits.info.pdest
-      wakeupQueue.io.in.bits.destType := Mux(in.bits.info.fpWen, SrcType.fp, Mux(in.bits.info.rfWen, SrcType.reg, SrcType.default))
+      wakeupQueue.io.in.bits.destType := Mux(in.bits.info.fpWen, SrcType.fp, Mux(in.bits.info.rfWen, SrcType.reg, SrcType.DC))
       wakeupQueue.io.redirect := redirect
       res := wakeupQueue.io.out
     } else {
-      res.valid := in.fire
+      res.valid := in.fire && (in.bits.info.fpWen || in.bits.info.rfWen)
       res.bits.lpv := in.bits.info.lpv
       res.bits.robPtr := in.bits.info.robPtr
       res.bits.pdest := in.bits.info.pdest
-      res.bits.destType := Mux(in.bits.info.fpWen, SrcType.fp, Mux(in.bits.info.rfWen, SrcType.reg, SrcType.default))
+      res.bits.destType := Mux(in.bits.info.fpWen, SrcType.fp, Mux(in.bits.info.rfWen, SrcType.reg, SrcType.DC))
     }
     res
   }

src/main/scala/xiangshan/backend/regfile/RegFileTop.scala

@@ -210,7 +210,6 @@ class RegFileTop(extraScalarRfReadPort: Int)(implicit p:Parameters) extends Lazy
           val isMaskDisabled = bi.issue.bits.uop.ctrl.vm && vmVal(uopIdx) === 0.U
           val isTailDisabled = bi.issue.bits.uop.isTail
           val isPrestartDisabled = bi.issue.bits.uop.isPrestart
-          exuInBundle.uop.loadStoreEnable := !(bi.issue.bits.uop.ctrl.isVector && (isMaskDisabled || isTailDisabled || isPrestartDisabled))
 
           //Base address read
           intRf.io.read(intRfReadIdx).addr := bi.issue.bits.uop.psrc(0)
@@ -234,7 +233,6 @@ class RegFileTop(extraScalarRfReadPort: Int)(implicit p:Parameters) extends Lazy
             io.vectorRfMoveReq(vecMoveReqPortIdx).bits.agnostic := false.B
             io.vectorRfMoveReq(vecMoveReqPortIdx).bits.enable := true.B
           }
-
           io.vectorRfMoveReq(vecMoveReqPortIdx).bits.srcAddr := bi.issue.bits.uop.psrc(2)
           io.vectorRfMoveReq(vecMoveReqPortIdx).bits.dstAddr := bi.issue.bits.uop.pdest
           io.vectorRfMoveReq(vecMoveReqPortIdx).bits.sew := bi.issue.bits.uop.vCsrInfo.vsew
@@ -275,6 +273,7 @@ class RegFileTop(extraScalarRfReadPort: Int)(implicit p:Parameters) extends Lazy
           }
           io.pcReadAddr(pcReadPortIdx) := bi.issue.bits.uop.cf.ftqPtr.value
           exuInBundle.uop.cf.pc := io.pcReadData(pcReadPortIdx).getPc(bi.issue.bits.uop.cf.ftqOffset)
+          exuInBundle.uop.loadStoreEnable := !(bi.issue.bits.uop.ctrl.isVector && (isMaskDisabled || isTailDisabled || isPrestartDisabled))
 
           intRfReadIdx = intRfReadIdx + 2
           fpRfReadIdx = fpRfReadIdx + 1

src/main/scala/xiangshan/backend/rob/Rob.scala

@@ -789,6 +789,7 @@ class RobImp(outer: Rob)(implicit p: Parameters) extends LazyModuleImp(outer)
       wdata.ftqOffset   := req.cf.ftqOffset
       wdata.vecWen      := req.ctrl.isVector
       wdata.wvcsr       := false.B
+      wdata.vtypeWb     := req.ctrl.isVtype
   }
 
   for(i <- 0 until fflagsWbNums) {

src/main/scala/xiangshan/backend/rob/WbCollector.scala

@@ -0,0 +1,59 @@
+/***************************************************************************************
+ * Copyright (c) 2020-2023 Institute of Computing Technology, Chinese Academy of Sciences
+ *
+ * XiangShan is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ *          http://license.coscl.org.cn/MulanPSL2
+ *
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ *
+ * See the Mulan PSL v2 for more details.
+ ***************************************************************************************/
+
+/***************************************************************************************
+ * Author: Liang Sen
+ * E-mail: [email protected]
+ * Date: 2023-06-19
+ ****************************************************************************************/
+
+package xiangshan.backend.rob
+
+import chisel3._
+import chisel3.util._
+import chipsalliance.rocketchip.config.Parameters
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
+
+import difftest._
+import utils._
+import xs.utils._
+import xiangshan._
+import xiangshan.frontend.FtqPtr
+import xiangshan.backend.execute.exu.{ExuConfig, ExuType}
+import xiangshan.backend.writeback._
+import xiangshan.vector._
+
+class WbCollector(implicit p: Parameters) extends LazyModule with HasXSParameter {
+  val wbNodeParamCommon = WriteBackSinkParam(name = "WbCommon", sinkType = WriteBackSinkType.rob)
+  val wbNodeParamMerge  = WriteBackSinkParam(name = "WbMerge", sinkType = WriteBackSinkType.vecMs)
+  val wbNodeCommon = new WriteBackSinkNode(wbNodeParamCommon)
+  val wbNodeMerge = new WriteBackSinkNode(wbNodeParamMerge)
+  lazy val module = new WbCollectorImp(this)
+}
+
+class WbCollectorImp(outer: WbCollector)(implicit p: Parameters) extends LazyModuleImp(outer)
+  with HasXSParameter
+  with HasVectorParameters {
+    val commonWbInBundles = outer.wbNodeCommon.in.head._1
+    val commonWbInParams = outer.wbNodeCommon.in.head._2._1
+    val commonWbIn = commonWbInParams zip commonWbInBundles
+
+    val mergeWbInBundles = outer.wbNodeMerge.in.head._1
+    val mergeWbInParams = outer.wbNodeMerge.in.head._2._1
+    val mergeWbIn = mergeWbInParams zip mergeWbInBundles
+
+    val wbCommonNums = commonWbIn.length
+    val wbMergeNums = mergeWbIn.length
+}

src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala

@@ -101,7 +101,7 @@ class LsqWrappper(implicit p: Parameters) extends XSModule with HasDCacheParamet
     val lsqVecDeqCnt = Output(new LsqVecDeqIO)
     val loadQueueDcache = new LQDcacheReqResp
     val storeQueueDcache = Flipped(new DCacheToSbufferIO)
-    val stout = Vec(2,Decoupled(new ExuOutput))
+    val stout = Vec(StorePipelineWidth,Decoupled(new ExuOutput))
   })
 
   val loadQueue = Module(new LoadQueue)

src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala

@@ -87,7 +87,7 @@ class StoreQueue(implicit p: Parameters) extends XSModule
     val storeVectorDeqCnt = Output(UInt(log2Up(StoreQueueSize + 1).W))
     val vectorOrderedFlushSBuffer = new SbufferFlushBundle
     val dcacheReqResp = Flipped(new DCacheToSbufferIO)
-    val stout = Vec(2,Decoupled(new ExuOutput))
+    val stout = Vec(StorePipelineWidth,Decoupled(new ExuOutput))
   })
   //
   io.storeVectorDeqCnt := 0.U
@@ -100,6 +100,7 @@ class StoreQueue(implicit p: Parameters) extends XSModule
   val dataModule = Module(new SQDataModule(
     numEntries = StoreQueueSize,
     numRead = StorePipelineWidth,
+    numWbRead = StorePipelineWidth, //for stout
     numWrite = StorePipelineWidth,
     numForward = StorePipelineWidth
   ))
@@ -115,7 +116,8 @@ class StoreQueue(implicit p: Parameters) extends XSModule
     PNumWrite = 0,
     VAddrWidth = VAddrBits,
     VNumRead = 1,
-    VNumWrite = 0
+    VNumWrite = 0,
+    WbNumRead = StorePipelineWidth  //for stout
   ))
   v_pAddrModule.io := DontCare
 
@@ -150,6 +152,7 @@ class StoreQueue(implicit p: Parameters) extends XSModule
   val committed = RegInit(VecInit(List.fill(StoreQueueSize)(false.B))) // inst has been committed by rob
   val pending = RegInit(VecInit(List.fill(StoreQueueSize)(false.B))) // mmio pending: inst is an mmio inst, it will not be executed until it reachs the end of rob
   val mmio = RegInit(VecInit(List.fill(StoreQueueSize)(false.B))) // mmio: inst is an mmio inst
+  val writebacked = RegInit(VecInit(List.fill(StoreQueueSize)(false.B)))  //inst has writebacked
 
   // ptr
   val enqPtrExt = RegInit(VecInit((0 until io.enq.req.length).map(_.U.asTypeOf(new SqPtr))))
@@ -232,6 +235,7 @@ class StoreQueue(implicit p: Parameters) extends XSModule
       addrvalid(index) := false.B
       committed(index) := false.B
       pending(index) := false.B
+      writebacked(index) := false.B
       XSError(!io.enq.canAccept || !io.enq.lqCanAccept, s"must accept $i\n")
       XSError(index =/= sqIdx.value, s"must be the same entry $i\n")
     }
@@ -632,14 +636,100 @@ class StoreQueue(implicit p: Parameters) extends XSModule
     dataBuffer.io.enq(i).bits.mask  := dataModule.io.rdata(i).mask
     dataBuffer.io.enq(i).bits.wline := v_pAddrModule.io.rlineflag_v_p(i)
     dataBuffer.io.enq(i).bits.sqPtr := rdataPtrExt(i)
+  }
+
+
+  def getEvenBits(input: UInt): UInt = {
+    VecInit((0 until StoreQueueSize / 2).map(i => {
+      input(2 * i)
+    })).asUInt
+  }
+
+  def getOddBits(input: UInt): UInt = {
+    VecInit((0 until StoreQueueSize / 2).map(i => {
+      input(2 * i + 1)
+    })).asUInt
+  }
+
+  def getFirstOne(mask: Vec[Bool], startMask: UInt) = {
+    val length = mask.length
+    val highBits = (0 until length).map(i => mask(i) & ~startMask(i))
+    val highBitsUint = Cat(highBits.reverse)
+    PriorityEncoder(Mux(highBitsUint.orR(), highBitsUint, mask.asUInt))
+  }
 
-    io.stout(i).valid := allocated(ptr) && committed(ptr) && !mmioStall
-    io.stout(i).bits := DontCare
-    io.stout(i).bits.uop := uop(ptr)
-    io.stout(i).bits.data := dataModule.io.rdata(i).data
-    io.stout(i).bits.wbmask := DontCare
+  def toVec(a: UInt): Vec[Bool] = {
+    VecInit(a.asBools)
   }
 
+  val storeWbSelV = Wire(Vec(StorePipelineWidth, Bool()))
+  val storeWbSel = Wire(Vec(LoadPipelineWidth,UInt(log2Up(StoreQueueSize).W)))
+
+  //s0 sel writeback index
+  val storeWbSelVec = VecInit((0 until StoreQueueSize).map(i => {
+    allocated(i) && allvalid(i) && !writebacked(i)
+  })).asUInt
+
+  val evenDeqMask = getEvenBits(deqMask)
+  val oddDeqMask = getOddBits(deqMask)
+
+  val evenFireMask = getEvenBits(UIntToOH(storeWbSel(0)))
+  val oddFireMask = getOddBits(UIntToOH(storeWbSel(1)))
+
+  val storeEvenSelVecFire = getEvenBits(storeWbSelVec) & ~evenFireMask
+  val storeOddSelVecFire = getOddBits(storeWbSelVec) & ~oddFireMask
+
+  val storeEvenSelVecNotFire = getEvenBits(storeWbSelVec)
+  val storeOddSelVecNotFire = getOddBits(storeWbSelVec)
+
+  val storeEvenSel = Mux(
+    io.stout(0).fire,
+    getFirstOne(toVec(storeEvenSelVecFire), evenDeqMask),
+    getFirstOne(toVec(storeEvenSelVecNotFire), evenDeqMask)
+  )
+
+  val storeOddSel = Mux(
+    io.stout(1).fire,
+    getFirstOne(toVec(storeOddSelVecFire), oddDeqMask),
+    getFirstOne(toVec(storeOddSelVecNotFire), oddDeqMask)
+  )
+
+  val storeWbSelGen = Wire(Vec(StorePipelineWidth,UInt(log2Up(StoreQueueSize).W)))
+  val storeWbSelVGen = Wire(Vec(StorePipelineWidth,Bool()))
+  storeWbSelGen(0) := Cat(storeEvenSel,0.U(1.W))
+  storeWbSelVGen(0) := Mux(io.stout(0).fire,storeEvenSelVecFire.asUInt.orR,storeEvenSelVecNotFire.asUInt.orR)
+  storeWbSelGen(1) := Cat(storeOddSel,1.U(1.W))
+  storeWbSelVGen(1) := Mux(io.stout(1).fire,storeOddSelVecFire.asUInt.orR,storeOddSelVecNotFire.asUInt.orR)
+
+  (0 until StorePipelineWidth).foreach({ case i => {
+    storeWbSel(i) := RegNext(storeWbSelGen(i))
+    storeWbSelV(i) := RegNext(storeWbSelVGen(i), false.B)
+    when(io.stout(i).fire){
+      writebacked(storeWbSel(i)) := true.B
+    }
+  }})
+
+
+  //s1 start writedback
+  (0 until StorePipelineWidth).foreach(i => {
+    dataModule.io.wbRead.raddr(i) := storeWbSelGen(i)
+    v_pAddrModule.io.wbRead.raddr(i) := storeWbSelGen(i)
+
+    val rdata = dataModule.io.wbRead.rdata(i).data
+    val seluop = uop(storeWbSel(i))
+    val raddr = v_pAddrModule.io.wbRead.paddr(i)
+
+
+    io.stout(i) := DontCare
+    io.stout(i).valid := storeWbSelV(i) && !io.stout(i).bits.uop.robIdx.needFlush((io.brqRedirect))
+    io.stout(i).bits.uop := seluop
+    io.stout(i).bits.data := rdata
+    io.stout(i).bits.redirectValid := false.B
+    io.stout(i).bits.redirect := DontCare
+  })
+
+
+
   // Send data stored in sbufferReqBitsReg to sbuffer
   for (i <- 0 until StorePipelineWidth) {
     io.sbuffer(i).valid := dataBuffer.io.deq(i).valid