GitHub - joel0/CprE281-FinalProj: Iowa State University code for Cpr E 281 (Digital Logic). This project is a 12-hour AM/PM alarm clock. This project is for an Altera FPGA development board using Quartus II.

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Iowa State University code for Cpr E 281 (Digital Logic). This project is a 12-hour AM/PM alarm clock. This project is for an Altera FPGA development board using Quartus II.

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Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
db		db
incremental_db		incremental_db
output_files		output_files
simulation/modelsim		simulation/modelsim
4bitUpDownCounter.bdf		4bitUpDownCounter.bdf
4bitUpDownCounter.bsf		4bitUpDownCounter.bsf
6bitUpDownCounter.bdf		6bitUpDownCounter.bdf
6bitUpDownCounter.bsf		6bitUpDownCounter.bsf
8bit_bcd_converter.bdf		8bit_bcd_converter.bdf
8bit_bcd_converter.bsf		8bit_bcd_converter.bsf
add3.bsf		add3.bsf
add3.v		add3.v
add3.v.bak		add3.v.bak
adder_4bit.bdf		adder_4bit.bdf
adder_4bit.bsf		adder_4bit.bsf
bcd_converter.v		bcd_converter.v
bcd_converter.v.bak		bcd_converter.v.bak
bcd_covnerter.bsf		bcd_covnerter.bsf
clkHalf.bdf		clkHalf.bdf
clkHalf.bsf		clkHalf.bsf
full_adder.bdf		full_adder.bdf
full_adder.bsf		full_adder.bsf
mainClock.bdf		mainClock.bdf
mainClock.bsf		mainClock.bsf
mainFSM.bdf		mainFSM.bdf
mainFSM.bsf		mainFSM.bsf
proj.bdf		proj.bdf
proj.jdi		proj.jdi
proj.qpf		proj.qpf
proj.qsf		proj.qsf
proj.qsf.bak		proj.qsf.bak
proj.qws		proj.qws
seven_seg_decoder.bsf		seven_seg_decoder.bsf
seven_seg_decoder.v		seven_seg_decoder.v
seven_seg_decoder.v.bak		seven_seg_decoder.v.bak

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Iowa State University code for Cpr E 281 (Digital Logic). This project is a 12-hour AM/PM alarm clock. This project is for an Altera FPGA development board using Quartus II.

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