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khkim6040 · May 12, 2024 · ea9d589 · ea9d589
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Showing 16 changed files with 150 additions and 130 deletions.
diff --git a/lab4-2/ALU.v b/lab4-2/ALU.v
@@ -7,7 +7,7 @@ module ALU (
     input [1:0] jump_signal,
     output reg [31:0] alu_result,
     output reg [1:0] alu_bcond
-);
+    );
 
     always @(*) begin
         alu_result = 32'b0;

diff --git a/lab4-2/ALUControlUnit.v b/lab4-2/ALUControlUnit.v
@@ -5,7 +5,7 @@ module ALUControlUnit (
     input [2:0] funct3,
     input [1:0] alu_op,
     output reg [3:0] alu_ctrl_out
-);
+    );
 
     always @(*) begin 
         case(alu_op) 

diff --git a/lab4-2/Adder.v b/lab4-2/Adder.v
@@ -1,6 +1,8 @@
-module Adder(input [31:0] x0,
-             input [31:0] x1,  
-             output reg [31:0] sum);
+module Adder(
+  input [31:0] x0,
+  input [31:0] x1,  
+  output reg [31:0] sum
+  );
 
 always@(*) begin
   sum = x0 + x1;

diff --git a/lab4-2/ControlUnit.v b/lab4-2/ControlUnit.v
@@ -1,15 +1,16 @@
 `include "opcodes.v"
 
-module ControlUnit (input [6:0] part_of_inst,
-                    output reg mem_read,
-                    output reg [1:0] mem_to_reg,
-                    output reg mem_write,
-                    output reg alu_src,
-                    output reg reg_write,
-                    output reg [1:0] alu_op,
-                    output reg is_ecall,
-                    output reg [1:0] jump_signal
-                    );
+module ControlUnit (
+    input [6:0] part_of_inst,
+    output reg mem_read,
+    output reg [1:0] mem_to_reg,
+    output reg mem_write,
+    output reg alu_src,
+    output reg reg_write,
+    output reg [1:0] alu_op,
+    output reg is_ecall,
+    output reg [1:0] jump_signal
+    );
 
 
     always @(*) begin

diff --git a/lab4-2/DataMemory.v b/lab4-2/DataMemory.v
@@ -1,10 +1,13 @@
-module DataMemory #(parameter MEM_DEPTH = 16384) (input reset,
-                                                  input clk,
-                                                  input [31:0] addr,    // address of the data memory
-                                                  input [31:0] din,     // data to be written
-                                                  input mem_read,       // is read signal driven?
-                                                  input mem_write,      // is write signal driven?
-                                                  output [31:0] dout);  // output of the data memory at addr
+module DataMemory #(parameter MEM_DEPTH = 16384) (
+  input reset,
+  input clk,
+  input [31:0] addr,    // address of the data memory
+  input [31:0] din,     // data to be written
+  input mem_read,       // is read signal driven?
+  input mem_write,      // is write signal driven?
+  output [31:0] dout    // output of the data memory at addr
+  );  
+
   integer i;
   // Data memory
   reg [31:0] mem[0: MEM_DEPTH - 1];

diff --git a/lab4-2/ForwardingUnit.v b/lab4-2/ForwardingUnit.v
@@ -8,7 +8,8 @@ module ForwardingUnit(
     input alu_src,
     output reg [1:0] forwardA,
     output reg [1:0] forwardB,
-    output reg [1:0] forwardC);
+    output reg [1:0] forwardC
+    );
 
     always @(*) begin
         if ((EX_rs1_index != 0) && (EX_rs1_index == MEM_reg_rd) && MEM_reg_write) 

diff --git a/lab4-2/GShare.v b/lab4-2/GShare.v
@@ -1,13 +1,14 @@
 `include "opcodes.v"
 
 module GShare(
-                input clk,
-                input reset,
-                input [31:0] pc,
-                input [1:0] bcond,
-                input [31:0] EX_correct_next_pc,
-                input [31:0] EX_pc,
-                output reg [31:0] next_pc);
+    input clk,
+    input reset,
+    input [31:0] pc,
+    input [1:0] bcond,
+    input [31:0] EX_correct_next_pc,
+    input [31:0] EX_pc,
+    output reg [31:0] next_pc
+    );
 
     reg [56:0] BTB [31:0];
     reg [4:0] BHSR;

diff --git a/lab4-2/HaltDetector.v b/lab4-2/HaltDetector.v
@@ -1,7 +1,8 @@
 module HaltDetector(
     input is_ecall,
-    input[31:0] rs1_data,
-    output reg is_halted);
+    input [31:0] rs1_data,
+    output reg is_halted
+    );
 
     always @(*) begin
         is_halted = is_ecall && (rs1_data == 10);

diff --git a/lab4-2/HazardDetector.v b/lab4-2/HazardDetector.v
@@ -1,23 +1,25 @@
 `include "opcodes.v"
 
-module HazardDetector (input clk,
-                       input reset,
-                       input [31:0] instruction,
-                       input [4:0] rs1,
-                       input [4:0] EX_rd,
-                       input [4:0] MEM_rd,
-                       input mem_read,
-                       input is_ecall,
-                       input [1:0] bcond,
-                       input [31:0] ID_PC,
-                       input [31:0] EX_PC,
-                       input [31:0] target_pc,
-                       output reg PC_write,
-                       output reg IF_ID_write,
-                       output reg ID_EX_nop_signal,
-                       output reg IF_ID_nop_signal,
-                       output reg [31:0] EX_correct_next_pc,
-                       output reg EX_PCSrc);
+module HazardDetector (
+    input clk,
+    input reset,
+    input [31:0] instruction,
+    input [4:0] rs1,
+    input [4:0] EX_rd,
+    input [4:0] MEM_rd,
+    input mem_read,
+    input is_ecall,
+    input [1:0] bcond,
+    input [31:0] ID_PC,
+    input [31:0] EX_PC,
+    input [31:0] target_pc,
+    output reg PC_write,
+    output reg IF_ID_write,
+    output reg ID_EX_nop_signal,
+    output reg IF_ID_nop_signal,
+    output reg [31:0] EX_correct_next_pc,
+    output reg EX_PCSrc
+    );
 
     reg [4:0] rs2;
     reg [6:0] opcode;

diff --git a/lab4-2/ImmediateGenerator.v b/lab4-2/ImmediateGenerator.v
@@ -3,7 +3,7 @@
 module ImmediateGenerator (
     input [31:0] part_of_inst,
     output reg [31:0] imm_gen_out
-);
+    );
 
     wire [6:0] opcode;
     wire [2:0] funct3;

diff --git a/lab4-2/InstMemory.v b/lab4-2/InstMemory.v
@@ -1,7 +1,10 @@
-module InstMemory #(parameter MEM_DEPTH = 1024) (input reset,
-                                                 input clk,
-                                                 input [31:0] addr,   // address of the instruction memory
-                                                 output [31:0] dout); // instruction at addr
+module InstMemory #(parameter MEM_DEPTH = 1024) (
+  input reset,
+  input clk,
+  input [31:0] addr,   // address of the instruction memory
+  output [31:0] dout   // instruction at addr
+  ); 
+
   integer i;
   // Instruction memory
   reg [31:0] mem[0:MEM_DEPTH - 1];

diff --git a/lab4-2/Mux_2_to_1.v b/lab4-2/Mux_2_to_1.v
@@ -2,7 +2,8 @@ module Mux_2_to_1 #(parameter WIDTH = 32) (
     input [WIDTH-1:0] x0,
     input [WIDTH-1:0] x1,
     input swch, 
-    output reg [WIDTH-1:0] out);
+    output reg [WIDTH-1:0] out
+    );
 
     always @(*) begin
     if (swch == 1'b0) begin

diff --git a/lab4-2/Mux_4_to_1.v b/lab4-2/Mux_4_to_1.v
@@ -1,9 +1,11 @@
-module Mux_4_to_1 (input [31:0] x0,
-        input [31:0] x1,
-        input [31:0] x2,
-        input [31:0] x3,
-        input [1:0] swch, 
-        output reg [31:0] out);
+module Mux_4_to_1 (
+    input [31:0] x0,
+    input [31:0] x1,
+    input [31:0] x2,
+    input [31:0] x3,
+    input [1:0] swch, 
+    output reg [31:0] out
+    );
 
     always @(*) begin
         case (swch)

diff --git a/lab4-2/PC.v b/lab4-2/PC.v
@@ -4,7 +4,7 @@ module PC(
     input [31:0] next_pc,
     input pc_write_signal,
     output reg [31:0] current_pc
-);
+    );
 
     always @(posedge clk) begin
         if (reset) begin

diff --git a/lab4-2/RegisterFile.v b/lab4-2/RegisterFile.v
@@ -1,13 +1,16 @@
-module RegisterFile(input	reset,
-                    input clk,
-                    input [4:0] rs1,          // source register 1
-                    input [4:0] rs2,          // source register 2
-                    input [4:0] rd,           // destination register
-                    input [31:0] rd_din,      // input data for rd
-                    input write_enable,       // RegWrite signal
-                    output [31:0] rs1_dout,   // output of rs 1
-                    output [31:0] rs2_dout,
-                    output [31:0] print_reg[0:31]);  // output of rs 2
+module RegisterFile(
+  input	reset,
+  input clk,
+  input [4:0] rs1,          // source register 1
+  input [4:0] rs2,          // source register 2
+  input [4:0] rd,           // destination register
+  input [31:0] rd_din,      // input data for rd
+  input write_enable,       // RegWrite signal
+  output [31:0] rs1_dout,   // output of rs 1
+  output [31:0] rs2_dout,
+  output [31:0] print_reg[0:31] // output of rs 2
+  );  
+
   integer i;
   // Register file
   reg [31:0] rf[0:31];