test,vcs: call $finish when difftest fails (OpenXiangShan#808)

src/test/csrc/vcs/main.cpp

@@ -20,9 +20,9 @@ extern "C" void simv_init() {
 
 }
 
-extern "C" void simv_step() {
-  if (assert_count > 0 || difftest_step()) {
-    printf("Difftest error\n");
-    exit(1);
+extern "C" int simv_step() {
+  if (assert_count > 0) {
+    return 1;
   }
+  return difftest_step();
 }

src/test/vsrc/vcs/top.v

@@ -1,12 +1,12 @@
 import "DPI-C" function void simv_init();
-import "DPI-C" function void simv_step();
+import "DPI-C" function int simv_step();
 
 module tb_top();
 
 reg         clock;
 reg         reset;
-wire [63:0] io_logCtrl_log_begin;
-wire [63:0] io_logCtrl_log_end;
+reg  [63:0] io_logCtrl_log_begin;
+reg  [63:0] io_logCtrl_log_end;
 wire [63:0] io_logCtrl_log_level;
 wire        io_perfInfo_clean;
 wire        io_perfInfo_dump;
@@ -18,11 +18,27 @@ wire [ 7:0] io_uart_in_ch;
 initial begin
   clock = 0;
   reset = 1;
-  #100 reset = 0;
+  // enable waveform
   if ($test$plusargs("dump-wave")) begin
     $vcdplusfile("simv.vpd");
     $vcdpluson;
   end
+  // log begin
+  if ($test$plusargs("b")) begin
+    $value$plusargs("b=%d", io_logCtrl_log_begin);
+  end
+  else begin
+    io_logCtrl_log_begin = 0;
+  end
+  // log end
+  if ($test$plusargs("e")) begin
+    $value$plusargs("e=%d", io_logCtrl_log_end);
+  end
+  else begin
+    io_logCtrl_log_end = 0;
+  end
+
+  #100 reset = 0;
 end
 always #1 clock <= ~clock;
 
@@ -40,16 +56,15 @@ SimTop sim(
   .io_uart_in_ch(io_uart_in_ch)
 );
 
-assign io_logCtrl_log_begin = 0;
-assign io_logCtrl_log_end = 0;
 assign io_logCtrl_log_level = 0;
 assign io_perfInfo_clean = 0;
 assign io_perfInfo_dump = 0;
 assign io_uart_in_ch = 8'hff;
 
 always @(posedge clock) begin
   if (!reset && io_uart_out_valid) begin
-    $write("%c", io_uart_out_ch);
+    $fwrite(32'h8000_0001, "%c", io_uart_out_ch);
+    $fflush();
   end
 end
 
@@ -63,9 +78,13 @@ always @(posedge clock) begin
     has_init <= 1'b1;
   end
 
+  // check errors
   if (!reset && has_init) begin
-    simv_step();
+    if (simv_step()) begin
+      $finish();
+    end
   end
+
 end
 
 endmodule

vcs.mk

@@ -13,12 +13,13 @@ VCS_BUILD_DIR  = $(abspath ./build/simv-compile)
 
 VCS_FLAGS += -full64 +v2k -timescale=1ns/1ns -sverilog -debug_access+all +lint=TFIPC-L
 # randomize all undefined signals (instead of using X)
-VCS_FLAGS += +define+RANDOMIZE_GARBAGE_ASSIGN +define+RANDOMIZE_INVALID_ASSIGN
-VCS_FLAGS += +define+RANDOMIZE_MEM_INIT +define+RANDOMIZE_DELAY=0 +define+RANDOMIZE_REG_INIT
+VCS_FLAGS += +vcs+initreg+random
+# VCS_FLAGS += +define+RANDOMIZE_GARBAGE_ASSIGN +define+RANDOMIZE_INVALID_ASSIGN
+# VCS_FLAGS += +define+RANDOMIZE_MEM_INIT +define+RANDOMIZE_DELAY=0 +define+RANDOMIZE_REG_INIT
 # SRAM lib defines
-VCS_FLAGS += +define+UNIT_DELAY +define+no_warning
+# VCS_FLAGS += +define+UNIT_DELAY +define+no_warning
 # C++ flags
-VCS_FLAGS += -CFLAGS "$(VCS_CXXFLAGS)" -LDFLAGS "$(VCS_LDFLAGS)"
+VCS_FLAGS += -CFLAGS "$(VCS_CXXFLAGS)" -LDFLAGS "$(VCS_LDFLAGS)" -j200
 # search build for other missing verilog files
 VCS_FLAGS += -y $(VCS_SEARCH_DIR) +libext+.v
 # build files put into $(VCS_BUILD_DIR)