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This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块:UART接收器、UART发送器、UART转AXI4交互式调试器。

Verilog 135 27 Updated Sep 14, 2023

A Fast, Low-Overhead On-chip Network

SystemVerilog 160 28 Updated Feb 3, 2025

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

SystemVerilog 467 116 Updated Nov 26, 2024

【典藏版】高清直播源涵盖几乎所有卫视节目,内置完美台标加节目预告

1,911 168 Updated Feb 7, 2025