TA's implementation for the project of Computer Architecture and Intelligent Chip Design (23 Spring)
Lab 1: ALU implementation
Lab 2: IF & ID stage implementation
Lab 3: Single-cycle RISC-V CPU implementation
Lab 4: 5-stage pipeline RISC-V CPU implementation (with data forwarding and branch forwarding to solve hazards)
Lab 5: Add L1 data cache for 5-stage pipeline CPU in Lab 4, and change the data ram into a slow-speed memory wrapper.