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Commits on Apr 20, 2023

• perf: add some slot util perf counters of id/rn/dp (OpenXiangShan#2046)

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Commits on Mar 16, 2023

• bump difftest, track master branch (OpenXiangShan#1967)

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Commits on Feb 21, 2023

• bump difftest & mkdir for wave/perf for local-ci script's run-mode (OpenXiangShan#1927)

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Commits on Feb 20, 2023

• debug: add local-ci.py to run github/emy.yml's ci tests at local server (OpenXiangShan#1925)

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Commits on Feb 14, 2023

• test: add example of chiseltest's unit-test and generating verilog for xs' module (OpenXiangShan#1890)

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Commits on Feb 13, 2023

• param: set EnableUncacheWriteOutstanding to false (OpenXiangShan#1913)

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Commits on Feb 11, 2023

• dtlb: set pf-tlb's ready to be True by default

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Commits on Feb 6, 2023

• CSR: fix wfi bug that writes csr OpenXiangShan#1891

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Commits on Dec 21, 2022

• l2tlb: fix bug that sfence fail to flush global sp entries (OpenXiangShan#1859)

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Commits on Nov 18, 2022

• l2tlb: add dup register & add blockhelper & llptw mem resp select timing optimization (OpenXiangShan#1752)

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Commits on Sep 15, 2022

• l2tlb: when ptw finish, re-access page cache to avoid dup-entries (OpenXiangShan#1781)

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Commits on Aug 12, 2022

• l2tlb: add some assert for repeater and l2tlb.cache's resp (OpenXiangShan#1734)

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Commits on Jul 27, 2022

• mmu.filter: add one more case for ptw resp filter (OpenXiangShan#1688)

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Commits on Jul 25, 2022

• l2tlb: add assert that do not allow duplicate mem access (OpenXiangShan#1669)

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• l1tlb: for non-block tlb port, resp should always be ready (OpenXiangShan#1673)

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Commits on Jul 21, 2022

• repeater: fix bug that drop reqs by last unenq reqs (OpenXiangShan#1672)

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• l1tlb: add ptw resp bypass logic & re-add multi-hit assert check (OpenXiangShan#1665)

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Commits on Jul 19, 2022

• l2tlb.cache: fix bug that read valid&data at different stage (OpenXiangShan#1663)

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Commits on Jul 18, 2022

• dtlb: change volume from s128f8 to s64f16 (OpenXiangShan#1662)

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• l1tlb: tlb's req port can be configured to be block or non-blocked (OpenXiangShan#1656)

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Commits on Jul 14, 2022

• dtlb: merge duplicated tlb together: one ld-tlb and one st-tlb. (OpenXiangShan#1654)

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• l1tlb: l1tlb entry uses one-hot size for timing optimization (OpenXiangShan#1626)

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Commits on Jul 9, 2022

• dtlb: replace sram with SyncDataModule (OpenXiangShan#1627)

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Commits on Jun 26, 2022

• l2tlb: add counter to ptw-filter to avoid l2tlb deadlock & sync sfence to mmu (OpenXiangShan#1599)

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Commits on Jun 25, 2022

• l2tlb: delay one cycle when read from sram (OpenXiangShan#1596)

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• tlb: divide v-select into two cycle for timing optimization (OpenXiangShan#1598)

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Commits on Jun 6, 2022

• util.sram: rm a r/w hazard mux which is not needed. bump huancun (OpenXiangShan#1571)

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Commits on May 21, 2022

• bump difftest, add vcs param for dump-wave and diff (OpenXiangShan#1557)

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Commits on Apr 14, 2022

• mmu.l2tlb: divide missqueue into 'missqueue' and llptw (OpenXiangShan#1522)

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Commits on Apr 1, 2022

• l2tlb.cache: store invalid entries(only super entries) into sp to avoid mem access waste (OpenXiangShan#1518)

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Commits on Mar 30, 2022

• sram-tlb: change SRAMTemplate & when tlb refill, just resp a miss/fast_miss (OpenXiangShan#1504)

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Commits on Feb 1, 2022

• l2tlb: req from missqueue doesn't cause prefetch (OpenXiangShan#1448)

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Commits on Jan 23, 2022

• pmp: fix bug of l locks cfg's modification (OpenXiangShan#1438)

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Commits on Dec 29, 2021

• csr: add one/two cycle for signals customCtrl/tlb/csrUpdate (OpenXiangShan#1405)

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Commits on Dec 26, 2021

• atomic: add static pmp relative modification (OpenXiangShan#1394)

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