[core] upgrading netlist generator

libs/libarchopenfpga/src/config_protocol.h

@@ -31,12 +31,14 @@ class ConfigProtocol {
  CircuitModelId memory_model() const;
  int num_regions() const;
 
+ /* Get information of the programming clock port: name and width */
+ openfpga::BasicPort prog_clock_port_info() const;
+ /* Get a list of programming clock pins, flatten from the programming clock port */
+ std::vector<openfpga::BasicPort> prog_clock_pins() const;
  /* Get a list of programming clock ports */
- std::vector<openfpga::BasicPort> prog_clock_ports() const;
- /* Get a list of programming clock ports */
- std::string prog_clock_port_ccff_head_indices_str(
+ std::string prog_clock_pin_ccff_head_indices_str(
  const openfpga::BasicPort& port) const;
- std::vector<size_t> prog_clock_port_ccff_head_indices(
+ std::vector<size_t> prog_clock_pin_ccff_head_indices(
  const openfpga::BasicPort& port) const;
 
  e_blwl_protocol_type bl_protocol_type() const;
@@ -54,10 +56,12 @@ class ConfigProtocol {
  void set_memory_model(const CircuitModelId& memory_model);
  void set_num_regions(const int& num_regions);
 
- /* Add a pair of programming clock port and ccff head indices. This API will
+ /* Add the programming clock port */
+ void set_prog_clock_port(const openfpga::BasicPort& port);
+ /* Add a pair of programming clock pin and ccff head indices. This API will
  * parse the index list, e.g., "0,1" to a vector of integers [0 1] */
- void set_prog_clock_port_ccff_head_indices_pair(
- const openfpga::BasicPort& port, const std::string& indices_str);
+ void set_prog_clock_pin_ccff_head_indices_pair(
+ const openfpga::BasicPort& pin, const std::string& indices_str);
 
  void set_bl_protocol_type(const e_blwl_protocol_type& type);
  void set_bl_memory_model_name(const std::string& memory_model_name);
@@ -99,8 +103,8 @@ class ConfigProtocol {
 
  /* Programming clock managment: This is only applicable to configuration chain
  * protocols */
- std::map<openfpga::BasicPort, std::vector<size_t>>
-   prog_clk_ccff_head_indices_;
+ BasicPort prog_clk_port_;
+ std::vector<std::vector<size_t>> prog_clk_ccff_head_indices_;
  char INDICE_STRING_DELIM_;
 
  /* BL & WL protocol: This is only applicable to memory-bank configuration

openfpga/src/fabric/build_top_module.cpp

@@ -595,14 +595,26 @@ int build_top_module(
  }
  }
 
+ /* For configuration chains, we avoid adding nets for programmable clocks if there are a few */
+ std::vector<std::string> global_port_blacklist;
+ if (config_protocol.num_prog_clocks() > 1) {
+ BasicPort prog_clk_port = config_protocol.prog_clock_port_info();
+ global_port_blacklist.push_back(prog_clk_port.get_name());
+ /* Add port */
+ ModulePortId port_id = module_manager.add_port(
+ module_id, prog_clk_port, ModuleManager::MODULE_GLOBAL_PORT);
+ /* Add nets by following configurable children under different regions */
+ add_top_module_nets_prog_clock(module_manager, top_module, port_id, config_protocol);
+ }
+
  /* Add global ports to the top module:
  * This is a much easier job after adding sub modules (instances),
  * we just need to find all the global ports from the child modules and build
  * a list of it
  * @note This function is called after the
  * add_top_module_nets_memory_config_bus() because it may add some sub modules
  */
- add_module_global_ports_from_child_modules(module_manager, top_module);
+ add_module_global_ports_from_child_modules(module_manager, top_module, global_port_blacklist);
 
  return status;
 }

openfpga/src/utils/module_manager_utils.cpp

@@ -2185,7 +2185,7 @@ void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager,
  * Otherwise, some global ports of the sub modules may be missed!
  *******************************************************************/
 void add_module_global_input_ports_from_child_modules(
- ModuleManager& module_manager, const ModuleId& module_id) {
+ ModuleManager& module_manager, const ModuleId& module_id, const std::vector<std::string>& port_name_to_ignore) {
  std::vector<BasicPort> global_ports_to_add;
 
  /* Iterate over the child modules */
@@ -2202,8 +2202,12 @@ void add_module_global_input_ports_from_child_modules(
  if (it != global_ports_to_add.end()) {
  continue;
  }
- /* Reach here, this is an unique global port, update the list */
- global_ports_to_add.push_back(global_port);
+ /* Reach here, this is an unique global port, update the list
+ * Final check: ignore those in the blacklist
+ */
+ if (std::find(port_name_to_ignore.begin(), port_name_to_ignore.end(), global_port.get_name()) == port_name_to_ignore.end()) {
+ global_ports_to_add.push_back(global_port);
+ }
  }
  }
  }
@@ -2304,9 +2308,10 @@ void add_module_global_input_ports_from_child_modules(
  * Otherwise, some global ports of the sub modules may be missed!
  *******************************************************************/
 void add_module_global_ports_from_child_modules(ModuleManager& module_manager,
- const ModuleId& module_id) {
+ const ModuleId& module_id,
+ const std::vector<std::string>& port_name_to_ignore) {
  /* Input ports */
- add_module_global_input_ports_from_child_modules(module_manager, module_id);
+ add_module_global_input_ports_from_child_modules(module_manager, module_id, port_name_to_ignore);
 }
 
 /********************************************************************

openfpga/src/utils/module_manager_utils.h

@@ -147,13 +147,15 @@ size_t find_module_num_config_bits(
  const e_config_protocol_type& sram_orgz_type);
 
 void add_module_global_input_ports_from_child_modules(
- ModuleManager& module_manager, const ModuleId& module_id);
+ ModuleManager& module_manager, const ModuleId& module_id,
+ const std::vector<std::string>& port_name_to_ignore = std::vector<std::string>());
 
 void add_module_global_output_ports_from_child_modules(
  ModuleManager& module_manager, const ModuleId& module_id);
 
 void add_module_global_ports_from_child_modules(ModuleManager& module_manager,
- const ModuleId& module_id);
+ const ModuleId& module_id,
+ const std::vector<std::string>& port_name_to_ignore = std::vector<std::string>());
 
 void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager,
  const ModuleId& module_id);