pass regression test when plug in refactored local encoders

lifpnc · Sep 10, 2019 · 5f561ef · 5f561ef
1 parent 62853c0
commit 5f561ef
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Showing 2 changed files with 4 additions and 4 deletions.
diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp
@@ -159,7 +159,7 @@ void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager,
 
  /* TODO: Generate modules into a .bak file now. Rename after it is verified */
  std::string verilog_fname(submodule_dir + local_encoder_verilog_file_name);
- verilog_fname += ".bak";
+ /* verilog_fname += ".bak"; */
 
  /* Create the file stream */
  std::fstream fp;
@@ -209,8 +209,6 @@ void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager,
  fp.close();
 
  /* TODO: Add fname to the linked list when debugging is finished */
- /*
- submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_name); 
- */
+ submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str()); 
 }
 
diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c
@@ -3559,8 +3559,10 @@ void dump_verilog_submodules(ModuleManager& module_manager,
  verilog_dir, submodule_dir);
 
  vpr_printf(TIO_MESSAGE_INFO, "Generating local encoders for multiplexers...\n");
+ /*
  dump_verilog_submodule_local_encoders(cur_sram_orgz_info, verilog_dir, submodule_dir, routing_arch->num_switch, 
  switch_inf, Arch.spice, routing_arch, fpga_verilog_opts.dump_explicit_verilog);
+ */
 
  print_verilog_submodule_mux_local_decoders(module_manager, mux_lib, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir));