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@BaudouinChauviere
BaudouinChauviere committed Jul 11, 2019
1 parent 31749fe commit f4be375
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Showing 5 changed files with 70 additions and 23 deletions.
3 changes: 2 additions & 1 deletion vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1340,7 +1340,8 @@ void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_clb2clb_directs(fp, num_clb2clb_directs, clb2clb_direct);

/* Dump configuration circuits */
dump_verilog_configuration_circuits(cur_sram_orgz_info, fp);
dump_verilog_configuration_circuits(cur_sram_orgz_info, fp,
is_explicit_mapping);

/* verilog ends*/
fprintf(fp, "endmodule\n");
Expand Down
50 changes: 36 additions & 14 deletions vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1132,7 +1132,7 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "%s_%d_ (", cur_interc->spice_model->prefix, cur_interc->spice_model->cnt);
cur_interc->spice_model->cnt++; /* Stats the number of spice_model used*/
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_interc->spice_model, FALSE, FALSE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_interc->spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
fprintf(fp, ",\n");
}
/* Print the pin names! Input and output
Expand All @@ -1143,11 +1143,24 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info,
/* Make sure correctness*/
assert(src_pb_type == des_pb_graph_pin->input_edges[iedge]->input_pins[0]->port->parent_pb_type);
/* Print */
fprintf(fp, "%s__%s_%d_, ",
if (true == is_explicit_mapping) {
fprintf(fp, ".in (");
}
fprintf(fp, "%s__%s_%d_",
src_pin_prefix, src_pb_graph_pin->port->name, src_pb_graph_pin->pin_number);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ", ");
/* Output */
fprintf(fp, "%s__%s_%d_ ",
if (true == is_explicit_mapping) {
fprintf(fp, ".out (");
}
fprintf(fp, "%s__%s_%d_",
des_pin_prefix, des_pb_graph_pin->port->name, des_pb_graph_pin->pin_number);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
/* Middle output for wires in logic blocks: TODO: Abolish to save simulation time */
/* fprintf(fp, "gidle_mid_out "); */
/* Local vdd and gnd, TODO: we should have an independent VDD for all local interconnections*/
Expand Down Expand Up @@ -1253,19 +1266,33 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "%s_size%d ", cur_interc->spice_model->name, fan_in);
fprintf(fp, "%s_size%d_%d_ (", cur_interc->spice_model->prefix, fan_in, cur_interc->spice_model->cnt);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_interc->spice_model, FALSE, FALSE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_interc->spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
fprintf(fp, ",\n");
}
/* Inputs */
fprintf(fp, "in_bus_%s_size%d_%d_, ",
if (true == is_explicit_mapping) {
fprintf(fp, ".in (");
}
fprintf(fp, "in_bus_%s_size%d_%d_",
cur_interc->spice_model->name, fan_in, cur_interc->spice_model->cnt);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ", ");
/* Generate the pin_prefix for src_pb_graph_node and des_pb_graph_node*/
if (true == is_explicit_mapping) {
fprintf(fp, ".out (");
}
generate_verilog_src_des_pb_graph_pin_prefix(src_pb_graph_pin, des_pb_graph_pin, pin2pin_interc_type,
cur_interc, formatted_parent_pin_prefix, &src_pin_prefix, &des_pin_prefix);
des_pin_prefix = chomp_verilog_prefix(des_pin_prefix);
/* Outputs */
fprintf(fp, "%s__%s_%d_, ",
fprintf(fp, "%s__%s_%d_",
des_pin_prefix, des_pb_graph_pin->port->name, des_pb_graph_pin->pin_number);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ", ");

/* Different design technology requires different configuration bus! */
dump_verilog_mux_config_bus_ports(fp, cur_interc->spice_model, cur_sram_orgz_info,
Expand Down Expand Up @@ -1849,13 +1876,8 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
/* Print inputs, outputs, inouts, clocks
* NO SRAMs !!! They have already been fixed in the bottom level
*/
bool is_explicit_full_name = true;
if (NULL != cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model){
/*if (SPICE_MODEL_HARDLOGIC == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model->type){
is_explicit_full_name = false;
}TEST*/
}
dump_verilog_pb_type_ports(fp, child_pb_type_prefix, 0, &(cur_pb_type->modes[mode_index].pb_type_children[ipb]), FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), is_explicit_full_name);
//}
dump_verilog_pb_type_ports(fp, child_pb_type_prefix, 0, &(cur_pb_type->modes[mode_index].pb_type_children[ipb]), FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), true);
/* Print I/O pads */
dump_verilog_grid_common_port(fp, iopad_verilog_model,
gio_inout_prefix,
Expand Down Expand Up @@ -1902,7 +1924,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
/* Print interconnections, set is_idle as TRUE*/
dump_verilog_pb_graph_interc(cur_sram_orgz_info, fp, subckt_name,
cur_pb_graph_node, mode_index,
false);
is_explicit_mapping);
/* Check each pins of pb_graph_node */
/* Check and update stamped_sram_cnt */
/* Now we only dump one Verilog for each pb_type, and instance them when num_pb > 1
Expand Down
33 changes: 28 additions & 5 deletions vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1069,7 +1069,8 @@ void dump_verilog_configuration_circuits_standalone_srams(t_sram_orgz_info* cur_
*/
static
void dump_verilog_configuration_circuits_scan_chains(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp) {
FILE* fp,
bool is_explicit_mapping) {
int num_mem_bits = 0;

/* Check */
Expand All @@ -1088,12 +1089,31 @@ void dump_verilog_configuration_circuits_scan_chains(t_sram_orgz_info* cur_sram_
verilog_config_peripheral_prefix,
verilog_config_peripheral_prefix);
/* Scan-chain input*/
if (true == is_explicit_mapping) {
fprintf(fp, ".%s (",
top_netlist_scan_chain_head_prefix);
}
dump_verilog_generic_port(fp, VERILOG_PORT_CONKT,
top_netlist_scan_chain_head_prefix, 0, 0);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ",\n");
if (true == is_explicit_mapping) {
fprintf(fp, ".scff_scff_in_local_bus (");
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, 0, num_mem_bits - 1, -1, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ",\n");
if (true == is_explicit_mapping) {
fprintf(fp, ".scff_scff_out_local_bus (");
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, 0, num_mem_bits - 1, 0, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ");\n");
fprintf(fp, "//------ END Configuration peripheral Scan-chain FFs -----\n");

Expand All @@ -1103,7 +1123,8 @@ void dump_verilog_configuration_circuits_scan_chains(t_sram_orgz_info* cur_sram_
/* Dump a memory bank to configure all the Bit lines and Word lines */
static
void dump_verilog_configuration_circuits_memory_bank(FILE* fp,
t_sram_orgz_info* cur_sram_orgz_info) {
t_sram_orgz_info* cur_sram_orgz_info,
bool is_explicit_mapping) {
int num_bl, num_wl;
int num_reserved_bl, num_reserved_wl;
int num_array_bl, num_array_wl;
Expand Down Expand Up @@ -1210,16 +1231,18 @@ void dump_verilog_configuration_circuits_memory_bank(FILE* fp,
* 3. Standalone SRAMs
*/
void dump_verilog_configuration_circuits(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp) {
FILE* fp,
bool is_explicit_mapping) {
switch(cur_sram_orgz_info->type) {
case SPICE_SRAM_STANDALONE:
dump_verilog_configuration_circuits_standalone_srams(cur_sram_orgz_info, fp);
break;
case SPICE_SRAM_SCAN_CHAIN:
dump_verilog_configuration_circuits_scan_chains(cur_sram_orgz_info, fp);
dump_verilog_configuration_circuits_scan_chains(cur_sram_orgz_info, fp, is_explicit_mapping);
break;
case SPICE_SRAM_MEMORY_BANK:
dump_verilog_configuration_circuits_memory_bank(fp, cur_sram_orgz_info);
/* BC: TODO explicit_mapping*/
dump_verilog_configuration_circuits_memory_bank(fp, cur_sram_orgz_info, is_explicit_mapping);
break;
default:
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type of SRAM organization in Verilog Generator!\n",
Expand Down
3 changes: 2 additions & 1 deletion vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.h
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Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,8 @@ void dump_verilog_clb2clb_directs(FILE* fp,
int num_directs, t_clb_to_clb_directs* direct);

void dump_verilog_configuration_circuits(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp);
FILE* fp,
bool is_explicit_mapping);

void dump_verilog_top_module_ports(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,
Expand Down
4 changes: 2 additions & 2 deletions vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2595,7 +2595,7 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m
* We do not need a prefix implying MUX name, size and index
*/
if (true == is_explicit_mapping) {
fprintf(fp, ".sram(");
fprintf(fp, ".sram (");
}
dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info,
mux_spice_model, mux_size,
Expand All @@ -2607,7 +2607,7 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m
}
fprintf(fp, ", ");
if (TRUE == is_explicit_mapping) {
fprintf(fp, ".sram_inv(");
fprintf(fp, ".sram_inv (");
}
dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info,
mux_spice_model, mux_size,
Expand Down

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