Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Fix placement of 32 bit regs on e500 and populate the low bits of PC on BE #702

Merged
merged 3 commits into from
Feb 28, 2024
Merged

Fix placement of 32 bit regs on e500 and populate the low bits of PC on BE #702

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
cd3a370
be fixes
2over12 Feb 28, 2024
07f8d7c
decriptive names
2over12 Feb 28, 2024
2a07ee5
fix tests
2over12 Feb 28, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
9 changes: 7 additions & 2 deletions include/remill/Arch/PPC/Runtime/State.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -27,13 +27,18 @@

struct Reg final {
union {
alignas(4) uint32_t dword;
struct {
alignas(4) uint32_t hi_bits;
alignas(4) uint32_t lo_bits;
} __attribute__((packed));
alignas(8) uint64_t qword;
} __attribute__((packed));
} __attribute__((packed));

static_assert(sizeof(uint64_t) == sizeof(Reg), "Invalid packing of `Reg`.");
static_assert(0 == __builtin_offsetof(Reg, dword),
static_assert(0 == __builtin_offsetof(Reg, hi_bits),
"Invalid packing of `Reg::dword`.");
static_assert(4 == __builtin_offsetof(Reg, lo_bits),
"Invalid packing of `Reg::dword`.");

static_assert(0 == __builtin_offsetof(Reg, qword),
Expand Down
66 changes: 33 additions & 33 deletions lib/Arch/Sleigh/PPCArch.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -165,38 +165,38 @@ class SleighPPCArch : public ArchBase {


// Subregs
SUB_REG(_R0, gpr.r0.dword, u32, R0);
SUB_REG(_R1, gpr.r1.dword, u32, R1);
SUB_REG(_R2, gpr.r2.dword, u32, R2);
SUB_REG(_R3, gpr.r3.dword, u32, R3);
SUB_REG(_R4, gpr.r4.dword, u32, R4);
SUB_REG(_R5, gpr.r5.dword, u32, R5);
SUB_REG(_R6, gpr.r6.dword, u32, R6);
SUB_REG(_R7, gpr.r7.dword, u32, R7);
SUB_REG(_R8, gpr.r8.dword, u32, R8);
SUB_REG(_R9, gpr.r9.dword, u32, R9);
SUB_REG(_R10, gpr.r10.dword, u32, R10);
SUB_REG(_R11, gpr.r11.dword, u32, R11);
SUB_REG(_R12, gpr.r12.dword, u32, R12);
SUB_REG(_R13, gpr.r13.dword, u32, R13);
SUB_REG(_R14, gpr.r14.dword, u32, R14);
SUB_REG(_R15, gpr.r15.dword, u32, R15);
SUB_REG(_R16, gpr.r16.dword, u32, R16);
SUB_REG(_R17, gpr.r17.dword, u32, R17);
SUB_REG(_R18, gpr.r18.dword, u32, R18);
SUB_REG(_R19, gpr.r19.dword, u32, R19);
SUB_REG(_R20, gpr.r20.dword, u32, R20);
SUB_REG(_R21, gpr.r21.dword, u32, R21);
SUB_REG(_R22, gpr.r22.dword, u32, R22);
SUB_REG(_R23, gpr.r23.dword, u32, R23);
SUB_REG(_R24, gpr.r24.dword, u32, R24);
SUB_REG(_R25, gpr.r25.dword, u32, R25);
SUB_REG(_R26, gpr.r26.dword, u32, R26);
SUB_REG(_R27, gpr.r27.dword, u32, R27);
SUB_REG(_R28, gpr.r28.dword, u32, R28);
SUB_REG(_R29, gpr.r29.dword, u32, R29);
SUB_REG(_R30, gpr.r30.dword, u32, R30);
SUB_REG(_R31, gpr.r31.dword, u32, R31);
SUB_REG(_R0, gpr.r0.lo_bits, u32, R0);
SUB_REG(_R1, gpr.r1.lo_bits, u32, R1);
SUB_REG(_R2, gpr.r2.lo_bits, u32, R2);
SUB_REG(_R3, gpr.r3.lo_bits, u32, R3);
SUB_REG(_R4, gpr.r4.lo_bits, u32, R4);
SUB_REG(_R5, gpr.r5.lo_bits, u32, R5);
SUB_REG(_R6, gpr.r6.lo_bits, u32, R6);
SUB_REG(_R7, gpr.r7.lo_bits, u32, R7);
SUB_REG(_R8, gpr.r8.lo_bits, u32, R8);
SUB_REG(_R9, gpr.r9.lo_bits, u32, R9);
SUB_REG(_R10, gpr.r10.lo_bits, u32, R10);
SUB_REG(_R11, gpr.r11.lo_bits, u32, R11);
SUB_REG(_R12, gpr.r12.lo_bits, u32, R12);
SUB_REG(_R13, gpr.r13.lo_bits, u32, R13);
SUB_REG(_R14, gpr.r14.lo_bits, u32, R14);
SUB_REG(_R15, gpr.r15.lo_bits, u32, R15);
SUB_REG(_R16, gpr.r16.lo_bits, u32, R16);
SUB_REG(_R17, gpr.r17.lo_bits, u32, R17);
SUB_REG(_R18, gpr.r18.lo_bits, u32, R18);
SUB_REG(_R19, gpr.r19.lo_bits, u32, R19);
SUB_REG(_R20, gpr.r20.lo_bits, u32, R20);
SUB_REG(_R21, gpr.r21.lo_bits, u32, R21);
SUB_REG(_R22, gpr.r22.lo_bits, u32, R22);
SUB_REG(_R23, gpr.r23.lo_bits, u32, R23);
SUB_REG(_R24, gpr.r24.lo_bits, u32, R24);
SUB_REG(_R25, gpr.r25.lo_bits, u32, R25);
SUB_REG(_R26, gpr.r26.lo_bits, u32, R26);
SUB_REG(_R27, gpr.r27.lo_bits, u32, R27);
SUB_REG(_R28, gpr.r28.lo_bits, u32, R28);
SUB_REG(_R29, gpr.r29.lo_bits, u32, R29);
SUB_REG(_R30, gpr.r30.lo_bits, u32, R30);
SUB_REG(_R31, gpr.r31.lo_bits, u32, R31);

REG(F0, fpr.f0.qword, f64);
REG(F1, fpr.f1.qword, f64);
Expand Down Expand Up @@ -233,7 +233,7 @@ class SleighPPCArch : public ArchBase {
REG(CRALL, iar.cr.qword, u64);
REG(CTR, iar.ctr.qword, u64);
REG(LR, iar.lr.qword, u64);
REG(XER, iar.xer.dword, u32);
REG(XER, iar.xer.qword, u64);
REG(SPEFCR, iar.spefscr.qword, u64);
REG(ACC, iar.acc.qword, u64);

Expand Down
10 changes: 6 additions & 4 deletions lib/BC/SleighLifter.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -963,16 +963,17 @@ class SleighLifter::PcodeToLLVMEmitIntoBlock {
return LiftStatus::kLiftedUnsupportedInstruction;
}


auto i1 = llvm::IntegerType::get(this->context, 1);
// TODO(Ian): this should probably technically be != 0
auto trunc_should_branch = bldr.CreateTrunc(
*should_branch, llvm::IntegerType::get(this->context, 1));
*should_branch, i1 );
if (!isVarnodeInConstantSpace(lhs)) {
// directs dont read the address of the variable, the offset is the jump
// TODO(Ian): handle other address spaces
auto jump_addr = this->replacement_cont.LiftOffsetOrReplace(
bldr, lhs, this->insn_lifter_parent.GetWordType());


auto orig_pc_value = this->GetNextPc(bldr);
//CHECK(pc_reg_param.has_value());
auto next_pc_value =
Expand Down Expand Up @@ -1802,10 +1803,11 @@ LiftStatus SleighLifter::LiftIntoBlockWithSleighState(
intoblock_builer.CreateLoad(this->GetWordType(), next_pc_ref);


intoblock_builer.CreateStore(this->decoder.LiftPcFromCurrPc(
intoblock_builer.CreateStore(intoblock_builer.CreateZExtOrTrunc( this->decoder.LiftPcFromCurrPc(
intoblock_builer, next_pc, inst.bytes.size(),
DecodingContext(context_values)),
DecodingContext(context_values)), pc_ref_type),
pc_ref);

intoblock_builer.CreateStore(
intoblock_builer.CreateAdd(
next_pc,
Expand Down
78 changes: 44 additions & 34 deletions tests/PPC/TestLifting.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -53,6 +53,9 @@ const static std::unordered_map<
[](PPCState &st) -> test_runner::RegisterValueRef {
return &st.gpr.r3.qword;
}},
{"_r3", [](PPCState &st) -> uint32_t * { return &st.gpr.r3.lo_bits; }},
{"_r4", [](PPCState &st) -> uint32_t * { return &st.gpr.r4.lo_bits; }},
{"_r5", [](PPCState &st) -> uint32_t * { return &st.gpr.r5.lo_bits; }},
{"r4",
[](PPCState &st) -> test_runner::RegisterValueRef {
return &st.gpr.r4.qword;
Expand Down Expand Up @@ -263,9 +266,12 @@ TEST(PPCVLELifts, PPCVLEDiv) {
std::string insn_data("\x7c\xa4\x1b\x96", 4);
TestOutputSpec<PPCState> spec(
0x12, insn_data, remill::Instruction::Category::kCategoryNormal,
{{"r4", uint64_t(0xcc)}, {"r3", uint64_t(0x7)}, {"pc", uint64_t(0x12)}},
{{"r5", uint64_t(0x1d)}, {"r4", uint64_t(0xcc)}, {"r3", uint64_t(0x7)}, {"pc", uint64_t(0x16)}},
reg_to_accessor);
{{"_r4", uint32_t(0xcc)}, {"_r3", uint32_t(0x7)}, {"pc", uint64_t(0x12)}},
{{"r5", uint64_t(0x1d)},
{"_r4", uint32_t(0xcc)},
{"_r3", uint32_t(0x7)},
{"pc", uint64_t(0x16)}},
reg_to_accessor);
TestSpecRunner<PPCState> runner(curr_context);
runner.RunTestSpec(spec, kVLEContext);
}
Expand Down Expand Up @@ -471,10 +477,10 @@ TEST(PPCVLELifts, PPCVLEStoreWord) {
TestOutputSpec<PPCState> spec(0x12, insn_data,
remill::Instruction::Category::kCategoryNormal,
{{"pc", uint64_t(0x12)},
{"r5", uint64_t(0x13371337)},
{"_r5", uint32_t(0x13371337)},
{"r4", uint64_t(0xdeadbee0)}},
{{"pc", uint64_t(0x12 + 4)},
{"r5", uint64_t(0x13371337)},
{"_r5", uint32_t(0x13371337)},
{"r4", uint64_t(0xdeadbee0)}},
reg_to_accessor);
spec.AddPrecWrite<uint32_t>(0xdeadbee0 + 0x10, 0x0);
Expand All @@ -489,12 +495,10 @@ TEST(PPCVLELifts, PPCVLELoadImmediate) {
llvm::LLVMContext curr_context;
// se_li r7, 0x7
std::string insn_data("\x48\x77", 2);
TestOutputSpec<PPCState> spec(0x12, insn_data, remill::Instruction::Category::kCategoryNormal,
{{"pc", uint64_t(0x12)},
{"r7", uint64_t(0x0)}},
{{"pc", uint64_t(0x14)},
{"r7", uint64_t(0x7)}},
reg_to_accessor);
TestOutputSpec<PPCState> spec(
0x12, insn_data, remill::Instruction::Category::kCategoryNormal,
{{"pc", uint64_t(0x12)}, {"r7", uint64_t(0x0)}},
{{"pc", uint64_t(0x14)}, {"r7", uint64_t(0x7)}}, reg_to_accessor);

TestSpecRunner<PPCState> runner(curr_context);
runner.RunTestSpec(spec, kVLEContext);
Expand Down Expand Up @@ -724,13 +728,15 @@ TEST(PPCVLELifts, PPCVLERotateLeftWordImmediateAndMask) {
// n >> 2 & 7
// (n & 31) >> 2
std::string insn_data("\x74\xa6\xf7\x7f", 4);
TestOutputSpec<PPCState> spec(
0x12, insn_data, remill::Instruction::Category::kCategoryNormal,
{{"pc", uint64_t(0x12)}, {"r5", uint64_t(0x1337)}, {"r6", uint64_t(0x0)}},
{{"pc", uint64_t(0x12 + 4)},
{"r5", uint64_t(0x1337)},
{"r6", uint64_t(0x5)}},
reg_to_accessor);
TestOutputSpec<PPCState> spec(0x12, insn_data,
remill::Instruction::Category::kCategoryNormal,
{{"pc", uint64_t(0x12)},
{"_r5", uint32_t(0x1337)},
{"r6", uint64_t(0x0)}},
{{"pc", uint64_t(0x12 + 4)},
{"_r5", uint32_t(0x1337)},
{"r6", uint64_t(0x5)}},
reg_to_accessor);

TestSpecRunner<PPCState> runner(curr_context);
runner.RunTestSpec(spec, kVLEContext);
Expand All @@ -741,13 +747,15 @@ TEST(PPCVLELifts, PPCVLEConvertDoubleFromSignedInteger) {
llvm::LLVMContext curr_context;
// efdcfsi r5, r4
std::string insn_data("\x10\xa0\x22\xf1", 4);
TestOutputSpec<PPCState> spec(
0x12, insn_data, remill::Instruction::Category::kCategoryNormal,
{{"pc", uint64_t(0x12)}, {"r4", uint64_t(0x1337)}, {"r5", uint64_t(0x0)}},
{{"pc", uint64_t(0x12 + 4)},
{"r4", uint64_t(0x1337)},
{"r5", uint64_t(0x40b3370000000000)}},
reg_to_accessor);
TestOutputSpec<PPCState> spec(0x12, insn_data,
remill::Instruction::Category::kCategoryNormal,
{{"pc", uint64_t(0x12)},
{"_r4", uint32_t(0x1337)},
{"r5", uint64_t(0x0)}},
{{"pc", uint64_t(0x12 + 4)},
{"_r4", uint32_t(0x1337)},
{"r5", uint64_t(0x40b3370000000000)}},
reg_to_accessor);

TestSpecRunner<PPCState> runner(curr_context);
runner.RunTestSpec(spec, kVLEContext);
Expand All @@ -758,13 +766,15 @@ TEST(PPCVLELifts, PPCVLEConvertFloatFromSignedInteger) {
llvm::LLVMContext curr_context;
// efscfsi r5, r4
std::string insn_data("\x10\xa0\x22\xd1", 4);
TestOutputSpec<PPCState> spec(
0x12, insn_data, remill::Instruction::Category::kCategoryNormal,
{{"pc", uint64_t(0x12)}, {"r4", uint64_t(0x1337)}, {"r5", uint64_t(0x0)}},
{{"pc", uint64_t(0x12 + 4)},
{"r4", uint64_t(0x1337)},
{"r5", uint64_t(0x4599b800)}},
reg_to_accessor);
TestOutputSpec<PPCState> spec(0x12, insn_data,
remill::Instruction::Category::kCategoryNormal,
{{"pc", uint64_t(0x12)},
{"_r4", uint32_t(0x1337)},
{"r5", uint64_t(0x0)}},
{{"pc", uint64_t(0x12 + 4)},
{"_r4", uint32_t(0x1337)},
{"r5", uint64_t(0x4599b800)}},
reg_to_accessor);

TestSpecRunner<PPCState> runner(curr_context);
runner.RunTestSpec(spec, kVLEContext);
Expand All @@ -778,10 +788,10 @@ TEST(PPCVLELifts, PPCVLEConvertFloatToSignedInteger) {
TestOutputSpec<PPCState> spec(0x12, insn_data,
remill::Instruction::Category::kCategoryNormal,
{{"pc", uint64_t(0x12)},
{"r4", uint64_t(0x4599b800)},
{"_r4", uint32_t(0x4599b800)},
{"r5", uint64_t(0x0)}},
{{"pc", uint64_t(0x12 + 4)},
{"r4", uint64_t(0x4599b800)},
{"_r4", uint32_t(0x4599b800)},
{"r5", uint64_t(0x1337)}},
reg_to_accessor);

Expand Down
Loading