machxo2: Misc tidying up

Signed-off-by: gatecat <[email protected]>
limingnefu · Feb 12, 2021 · 6de733b · 6de733b
1 parent 33eca9a
commit 6de733b
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Showing 2 changed files with 4 additions and 8 deletions.
diff --git a/machxo2/arch.cc b/machxo2/arch.cc
@@ -401,7 +401,10 @@ delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
 ArcBounds Arch::getRouteBoundingBox(WireId src, WireId dst) const
 {
     ArcBounds bb;
-
+    bb.x0 = std::min(src.location.x, dst.location.x);
+    bb.y0 = std::min(src.location.y, dst.location.y);
+    bb.x1 = std::max(src.location.x, dst.location.x);
+    bb.y1 = std::max(src.location.y, dst.location.y);
     return bb;
 }
 

diff --git a/machxo2/archdefs.h b/machxo2/archdefs.h
@@ -129,13 +129,6 @@ struct NetInfo;
 
 struct ArchCellInfo
 {
-    // Custom grouping set via "PACK_GROUP" attribute. All cells with the same group
-    // value may share a tile (-1 = don't care, default if not set)
-    int user_group;
-    // Is a slice type primitive
-    bool is_slice;
-    // Only packing rule for slice type primitives is a single clock per tile
-    const NetInfo *slice_clk;
 };
 
 NEXTPNR_NAMESPACE_END