Amplication brings order to the chaos of large-scale software development by creating Golden Paths for developers - streamlined workflows that drive consistency, enable high-quality code practices,…

Stable Diffusion web UI

PicoGK is a compact and robust geometry kernel for Computational Engineering

[SIGIR'2024] "GraphGPT: Graph Instruction Tuning for Large Language Models"

Code for iccv2019 paper "A Neural Network for Detailed Human Depth Estimation from a Single Image"

A generic post-processing injector for games and video software.

With Vertex AI NAS, you can search for optimal neural architectures in terms of accuracy, latency, memory, a combination of these, or a custom metric.

Python Fire is a library for automatically generating command line interfaces (CLIs) from absolutely any Python object.

Temporian is an open-source Python library for preprocessing ⚡ and feature engineering 🛠 temporal data 📈 for machine learning applications 🤖

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using…

This repo turns your PC into a AI Horde worker node

For GGUF support, see KoboldCPP: https://github.com/LostRuins/koboldcpp

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

An implementation of model parallel autoregressive transformers on GPUs, based on the Megatron and DeepSpeed libraries

Implementation of Imagen, Google's Text-to-Image Neural Network, in Pytorch

CLIP + FFT/DWT/RGB = text to image/video

An optimized neural network operator library for chips base on Xuantie CPU.

OpenXuantie - OpenC910 Core

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

Assemble 128-bit RISC-V

3D computer vision incuding SLAM，VSALM，Deep Learning，Structured light，Stereo，Three-dimensional reconstruction，Computer vision，Machine Learning and so on

Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog

Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL

RiscyOO: RISC-V Out-of-Order Processor

RISC-V Cores, SoC platforms and SoCs