kconfig: Rename CONFIG_FLOAT to CONFIG_FPU

This commit renames the Kconfig `FLOAT` symbol to `FPU`, since this symbol only indicates that the hardware Floating Point Unit (FPU) is used and does not imply and/or indicate the general availability of toolchain-level floating point support (i.e. this symbol is not selected when building for an FPU-less platform that supports floating point operations through the toolchain-provided software floating point library). Moreover, given that the symbol that indicates the availability of FPU is named `CPU_HAS_FPU`, it only makes sense to use "FPU" in the name of the symbol that enables the FPU. Signed-off-by: Stephanos Ioannidis <[email protected]>
lmaciejonczyk · Apr 27, 2020 · 0e6ede8 · 0e6ede8
1 parent 3230a85
commit 0e6ede8
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Showing 56 changed files with 114 additions and 115 deletions.
diff --git a/arch/Kconfig b/arch/Kconfig
@@ -520,7 +520,7 @@ config MPU_GAP_FILLING
 	  documentation for more information on how this option is
 	  used.
 
-menuconfig FLOAT
+menuconfig FPU
 	bool "Floating point"
 	depends on CPU_HAS_FPU
 	depends on ARC || ARM || RISCV || X86
@@ -533,7 +533,7 @@ menuconfig FLOAT
 
 config FP_SHARING
 	bool "Floating point register sharing"
-	depends on FLOAT
+	depends on FPU
 	help
 	  This option allows multiple threads to use the floating point
 	  registers.

diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
@@ -211,7 +211,7 @@ config CODE_DENSITY
 
 config ARC_HAS_ACCL_REGS
 	bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6)"
-	default y if FLOAT
+	default y if FPU
 	help
 	  Depending on the configuration, CPU can contain accumulator reg-pair
 	  (also referred to as r58:r59). These can also be used by gcc as GPR so

diff --git a/arch/arc/core/thread.c b/arch/arc/core/thread.c
@@ -274,7 +274,7 @@ FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry,
 
 #endif
 
-#if defined(CONFIG_FLOAT) && defined(CONFIG_FP_SHARING)
+#if defined(CONFIG_FPU) && defined(CONFIG_FP_SHARING)
 int arch_float_disable(struct k_thread *thread)
 {
 	unsigned int key;
@@ -307,4 +307,4 @@ int arch_float_enable(struct k_thread *thread)
 
 	return 0;
 }
-#endif /* CONFIG_FLOAT && CONFIG_FP_SHARING */
+#endif /* CONFIG_FPU && CONFIG_FP_SHARING */
diff --git a/arch/arm/core/aarch32/Kconfig b/arch/arm/core/aarch32/Kconfig
@@ -214,7 +214,7 @@ config ARM_NONSECURE_FIRMWARE
 choice
 	prompt "Floating point ABI"
 	default FP_HARDABI
-	depends on FLOAT
+	depends on FPU
 
 config FP_HARDABI
 	bool "Floating point Hard ABI"

diff --git a/arch/arm/core/aarch32/cortex_a_r/reset.S b/arch/arm/core/aarch32/cortex_a_r/reset.S
@@ -111,7 +111,7 @@ SECTION_SUBSEC_FUNC(TEXT, _reset_section, __start)
     mov r13, #0         /* r13_sys */
     mov r14, #0         /* r14_sys */
 
-#if defined(CONFIG_FLOAT)
+#if defined(CONFIG_FPU)
     /*
      * Initialise FPU registers to a defined state.
      */
@@ -142,7 +142,7 @@ SECTION_SUBSEC_FUNC(TEXT, _reset_section, __start)
     fmdrr d13, r1, r1
     fmdrr d14, r1, r1
     fmdrr d15, r1, r1
-#endif /* CONFIG_FLOAT */
+#endif /* CONFIG_FPU */
 
 #endif /* CONFIG_CPU_HAS_DCLS */
 

diff --git a/arch/arm/core/aarch32/cortex_m/mpu/arm_core_mpu.c b/arch/arm/core/aarch32/cortex_m/mpu/arm_core_mpu.c
@@ -215,7 +215,7 @@ void z_arm_configure_dynamic_mpu_regions(struct k_thread *thread)
 	u32_t guard_start;
 	u32_t guard_size = MPU_GUARD_ALIGN_AND_SIZE;
 
-#if defined(CONFIG_FLOAT) && defined(CONFIG_FP_SHARING)
+#if defined(CONFIG_FPU) && defined(CONFIG_FP_SHARING)
 	if ((thread->base.user_options & K_FP_REGS) != 0) {
 		guard_size = MPU_GUARD_ALIGN_AND_SIZE_FLOAT;
 	}

diff --git a/arch/arm/core/aarch32/fatal.c b/arch/arm/core/aarch32/fatal.c
@@ -23,7 +23,7 @@ static void esf_dump(const z_arch_esf_t *esf)
 	LOG_ERR("r3/a4:  0x%08x r12/ip:  0x%08x r14/lr:  0x%08x",
 		esf->basic.a4, esf->basic.ip, esf->basic.lr);
 	LOG_ERR(" xpsr:  0x%08x", esf->basic.xpsr);
-#if defined(CONFIG_FLOAT) && defined(CONFIG_FP_SHARING)
+#if defined(CONFIG_FPU) && defined(CONFIG_FP_SHARING)
 	for (int i = 0; i < 16; i += 4) {
 		LOG_ERR("s[%2d]:  0x%08x  s[%2d]:  0x%08x"
 			"  s[%2d]:  0x%08x  s[%2d]:  0x%08x",

diff --git a/arch/arm/core/aarch32/prep_c.c b/arch/arm/core/aarch32/prep_c.c
@@ -86,7 +86,7 @@ static inline void z_arm_floating_point_init(void)
 	 */
 	SCB->CPACR &= (~(CPACR_CP10_Msk | CPACR_CP11_Msk));
 
-#if defined(CONFIG_FLOAT)
+#if defined(CONFIG_FPU)
 	/*
 	 * Enable CP10 and CP11 Co-Processors to enable access to floating
 	 * point registers.
@@ -143,7 +143,7 @@ static inline void z_arm_floating_point_init(void)
 	 * of floating point instructions.
 	 */
 
-#endif /* CONFIG_FLOAT */
+#endif /* CONFIG_FPU */
 
 	/*
 	 * Upon reset, the CONTROL.FPCA bit is, normally, cleared. However,
@@ -154,7 +154,7 @@ static inline void z_arm_floating_point_init(void)
 	 * In Sharing FP Registers mode CONTROL.FPCA is cleared before switching
 	 * to main, so it may be skipped here (saving few boot cycles).
 	 */
-#if !defined(CONFIG_FLOAT) || !defined(CONFIG_FP_SHARING)
+#if !defined(CONFIG_FPU) || !defined(CONFIG_FP_SHARING)
 	__set_CONTROL(__get_CONTROL() & (~(CONTROL_FPCA_Msk)));
 #endif
 }

diff --git a/arch/arm/core/aarch32/thread.c b/arch/arm/core/aarch32/thread.c
@@ -71,7 +71,7 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
 	stackSize -= MPU_GUARD_ALIGN_AND_SIZE;
 #endif
 
-#if defined(CONFIG_FLOAT) && defined(CONFIG_FP_SHARING) \
+#if defined(CONFIG_FPU) && defined(CONFIG_FP_SHARING) \
 	&& defined(CONFIG_MPU_STACK_GUARD)
 	/* For a thread which intends to use the FP services, it is required to
 	 * allocate a wider MPU guard region, to always successfully detect an
@@ -166,13 +166,13 @@ FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry,
 	 * privileged stack. Adjust the available (writable) stack
 	 * buffer area accordingly.
 	 */
-#if defined(CONFIG_FLOAT) && defined(CONFIG_FP_SHARING)
+#if defined(CONFIG_FPU) && defined(CONFIG_FP_SHARING)
 	_current->arch.priv_stack_start +=
 		(_current->base.user_options & K_FP_REGS) ?
 		MPU_GUARD_ALIGN_AND_SIZE_FLOAT : MPU_GUARD_ALIGN_AND_SIZE;
 #else
 	_current->arch.priv_stack_start += MPU_GUARD_ALIGN_AND_SIZE;
-#endif /* CONFIG_FLOAT && CONFIG_FP_SHARING */
+#endif /* CONFIG_FPU && CONFIG_FP_SHARING */
 #endif /* CONFIG_MPU_STACK_GUARD */
 
 	z_arm_userspace_enter(user_entry, p1, p2, p3,
@@ -285,12 +285,12 @@ u32_t z_check_thread_stack_fail(const u32_t fault_addr, const u32_t psp)
 		return 0;
 	}
 
-#if defined(CONFIG_FLOAT) && defined(CONFIG_FP_SHARING)
+#if defined(CONFIG_FPU) && defined(CONFIG_FP_SHARING)
 	u32_t guard_len = (thread->base.user_options & K_FP_REGS) ?
 		MPU_GUARD_ALIGN_AND_SIZE_FLOAT : MPU_GUARD_ALIGN_AND_SIZE;
 #else
 	u32_t guard_len = MPU_GUARD_ALIGN_AND_SIZE;
-#endif /* CONFIG_FLOAT && CONFIG_FP_SHARING */
+#endif /* CONFIG_FPU && CONFIG_FP_SHARING */
 
 #if defined(CONFIG_USERSPACE)
 	if (thread->arch.priv_stack_start) {
@@ -333,7 +333,7 @@ u32_t z_check_thread_stack_fail(const u32_t fault_addr, const u32_t psp)
 }
 #endif /* CONFIG_MPU_STACK_GUARD || CONFIG_USERSPACE */
 
-#if defined(CONFIG_FLOAT) && defined(CONFIG_FP_SHARING)
+#if defined(CONFIG_FPU) && defined(CONFIG_FP_SHARING)
 int arch_float_disable(struct k_thread *thread)
 {
 	if (thread != _current) {
@@ -365,14 +365,14 @@ int arch_float_disable(struct k_thread *thread)
 
 	return 0;
 }
-#endif /* CONFIG_FLOAT && CONFIG_FP_SHARING */
+#endif /* CONFIG_FPU && CONFIG_FP_SHARING */
 
 void arch_switch_to_main_thread(struct k_thread *main_thread,
 				k_thread_stack_t *main_stack,
 				size_t main_stack_size,
 				k_thread_entry_t _main)
 {
-#if defined(CONFIG_FLOAT)
+#if defined(CONFIG_FPU)
 	/* Initialize the Floating Point Status and Control Register when in
 	 * Unshared FP Registers mode (In Shared FP Registers mode, FPSCR is
 	 * initialized at thread creation for threads that make use of the FP).
@@ -383,7 +383,7 @@ void arch_switch_to_main_thread(struct k_thread *main_thread,
 	__set_CONTROL(__get_CONTROL() & (~(CONTROL_FPCA_Msk)));
 	__ISB();
 #endif /* CONFIG_FP_SHARING */
-#endif /* CONFIG_FLOAT */
+#endif /* CONFIG_FPU */
 
 #ifdef CONFIG_ARM_MPU
 	/* Configure static memory map. This will program MPU regions,

diff --git a/arch/arm/core/offsets/offsets_aarch32.c b/arch/arm/core/offsets/offsets_aarch32.c
@@ -36,7 +36,7 @@ GEN_OFFSET_SYM(_thread_arch_t, priv_stack_start);
 #endif
 #endif
 
-#if defined(CONFIG_FLOAT) && defined(CONFIG_FP_SHARING)
+#if defined(CONFIG_FPU) && defined(CONFIG_FP_SHARING)
 GEN_OFFSET_SYM(_thread_arch_t, preempt_float);
 #endif
 
@@ -49,7 +49,7 @@ GEN_OFFSET_SYM(_basic_sf_t, lr);
 GEN_OFFSET_SYM(_basic_sf_t, pc);
 GEN_OFFSET_SYM(_basic_sf_t, xpsr);
 
-#if defined(CONFIG_FLOAT) && defined(CONFIG_FP_SHARING)
+#if defined(CONFIG_FPU) && defined(CONFIG_FP_SHARING)
 GEN_OFFSET_SYM(_esf_t, s);
 GEN_OFFSET_SYM(_esf_t, fpscr);
 #endif
@@ -82,7 +82,7 @@ GEN_ABSOLUTE_SYM(___thread_stack_info_t_SIZEOF,
  * point registers.
  */
 
-#if defined(CONFIG_FLOAT) && defined(CONFIG_FP_SHARING)
+#if defined(CONFIG_FPU) && defined(CONFIG_FP_SHARING)
 GEN_ABSOLUTE_SYM(_K_THREAD_NO_FLOAT_SIZEOF, sizeof(struct k_thread) -
 					    sizeof(struct _preempt_float));
 #else

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
@@ -16,7 +16,7 @@ config COMPRESSED_ISA
 config FLOAT_HARD
 	bool "Enable hard-float calling convention"
 	default y
-	depends on FLOAT
+	depends on FPU
 	select COMPRESSED_ISA
 	help
 	  This option enables the hard-float calling convention.

diff --git a/arch/riscv/core/isr.S b/arch/riscv/core/isr.S
@@ -144,7 +144,7 @@ SECTION_FUNC(exception.entry, __irq_wrapper)
 	RV_OP_STOREREG a6, __z_arch_esf_t_a6_OFFSET(sp)
 	RV_OP_STOREREG a7, __z_arch_esf_t_a7_OFFSET(sp)
 
-#if defined(CONFIG_FLOAT) && defined(CONFIG_FP_SHARING)
+#if defined(CONFIG_FPU) && defined(CONFIG_FP_SHARING)
 	/* Assess whether floating-point registers need to be saved. */
 	la t0, _kernel
 	RV_OP_LOADREG t0, _kernel_offset_to_current(t0)
@@ -396,7 +396,7 @@ reschedule:
 	RV_OP_STOREREG s10, _thread_offset_to_s10(t1)
 	RV_OP_STOREREG s11, _thread_offset_to_s11(t1)
 
-#if defined(CONFIG_FLOAT) && defined(CONFIG_FP_SHARING)
+#if defined(CONFIG_FPU) && defined(CONFIG_FP_SHARING)
 	/* Assess whether floating-point registers need to be saved. */
 	RV_OP_LOADREG t2, _thread_offset_to_user_options(t1)
 	andi t2, t2, K_FP_REGS
@@ -440,7 +440,7 @@ skip_store_fp_callee_saved:
 	RV_OP_LOADREG s10, _thread_offset_to_s10(t1)
 	RV_OP_LOADREG s11, _thread_offset_to_s11(t1)
 
-#if defined(CONFIG_FLOAT) && defined(CONFIG_FP_SHARING)
+#if defined(CONFIG_FPU) && defined(CONFIG_FP_SHARING)
 	/* Determine if we need to restore floating-point registers. */
 	RV_OP_LOADREG t2, _thread_offset_to_user_options(t1)
 	andi t2, t2, K_FP_REGS
@@ -482,7 +482,7 @@ skip_load_fp_callee_saved:
 	RV_OP_STOREREG a6, __z_arch_esf_t_a6_OFFSET(sp)
 	RV_OP_STOREREG a7, __z_arch_esf_t_a7_OFFSET(sp)
 
-#if defined(CONFIG_FLOAT) && defined(CONFIG_FP_SHARING)
+#if defined(CONFIG_FPU) && defined(CONFIG_FP_SHARING)
 	/* Assess whether floating-point registers need to be saved. */
 	RV_OP_LOADREG t2, _thread_offset_to_user_options(sp)
 	andi t2, t2, K_FP_REGS
@@ -495,7 +495,7 @@ skip_store_fp_caller_saved_benchmark:
 
 	call read_timer_end_of_swap
 
-#if defined(CONFIG_FLOAT) && defined(CONFIG_FP_SHARING)
+#if defined(CONFIG_FPU) && defined(CONFIG_FP_SHARING)
 	/* Determine if we need to restore floating-point registers. */
 	RV_OP_LOADREG t2, __z_arch_esf_t_fp_state_OFFSET(sp)
 	beqz t2, skip_load_fp_caller_saved_benchmark
@@ -542,7 +542,7 @@ no_reschedule:
 	RV_OP_LOADREG t0, __z_arch_esf_t_mstatus_OFFSET(sp)
 	csrw mstatus, t0
 
-#if defined(CONFIG_FLOAT) && defined(CONFIG_FP_SHARING)
+#if defined(CONFIG_FPU) && defined(CONFIG_FP_SHARING)
 	/*
 	 * Determine if we need to restore floating-point registers. This needs
 	 * to happen before restoring integer registers to avoid stomping on

diff --git a/arch/riscv/core/offsets/offsets.c b/arch/riscv/core/offsets/offsets.c
@@ -43,7 +43,7 @@ GEN_OFFSET_SYM(_callee_saved_t, s9);
 GEN_OFFSET_SYM(_callee_saved_t, s10);
 GEN_OFFSET_SYM(_callee_saved_t, s11);
 
-#if defined(CONFIG_FLOAT) && defined(CONFIG_FP_SHARING)
+#if defined(CONFIG_FPU) && defined(CONFIG_FP_SHARING)
 GEN_OFFSET_SYM(_callee_saved_t, fcsr);
 GEN_OFFSET_SYM(_callee_saved_t, fs0);
 GEN_OFFSET_SYM(_callee_saved_t, fs1);
@@ -82,7 +82,7 @@ GEN_OFFSET_SYM(z_arch_esf_t, a7);
 GEN_OFFSET_SYM(z_arch_esf_t, mepc);
 GEN_OFFSET_SYM(z_arch_esf_t, mstatus);
 
-#if defined(CONFIG_FLOAT) && defined(CONFIG_FP_SHARING)
+#if defined(CONFIG_FPU) && defined(CONFIG_FP_SHARING)
 GEN_OFFSET_SYM(z_arch_esf_t, fp_state);
 GEN_OFFSET_SYM(z_arch_esf_t, ft0);
 GEN_OFFSET_SYM(z_arch_esf_t, ft1);

diff --git a/arch/riscv/core/reset.S b/arch/riscv/core/reset.S
@@ -46,7 +46,7 @@ loop_slave_core:
 
 boot_master_core:
 
-#ifdef CONFIG_FLOAT
+#ifdef CONFIG_FPU
 	/*
 	 * Enable floating-point.
 	 */

diff --git a/arch/riscv/core/thread.c b/arch/riscv/core/thread.c
@@ -57,7 +57,7 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
 	 *    thread stack.
 	 */
 	stack_init->mstatus = MSTATUS_DEF_RESTORE;
-#if defined(CONFIG_FLOAT) && defined(CONFIG_FP_SHARING)
+#if defined(CONFIG_FPU) && defined(CONFIG_FP_SHARING)
 	if ((thread->base.user_options & K_FP_REGS) != 0) {
 		stack_init->mstatus |= MSTATUS_FS_INIT;
 	}
@@ -68,7 +68,7 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
 	thread->callee_saved.sp = (ulong_t)stack_init;
 }
 
-#if defined(CONFIG_FLOAT) && defined(CONFIG_FP_SHARING)
+#if defined(CONFIG_FPU) && defined(CONFIG_FP_SHARING)
 int arch_float_disable(struct k_thread *thread)
 {
 	unsigned int key;
@@ -131,4 +131,4 @@ int arch_float_enable(struct k_thread *thread)
 
 	return 0;
 }
-#endif /* CONFIG_FLOAT && CONFIG_FP_SHARING */
+#endif /* CONFIG_FPU && CONFIG_FP_SHARING */
diff --git a/arch/riscv/include/offsets_short_arch.h b/arch/riscv/include/offsets_short_arch.h
@@ -59,7 +59,7 @@
 #define _thread_offset_to_swap_return_value \
 	(___thread_t_arch_OFFSET + ___thread_arch_t_swap_return_value_OFFSET)
 
-#if defined(CONFIG_FLOAT) && defined(CONFIG_FP_SHARING)
+#if defined(CONFIG_FPU) && defined(CONFIG_FP_SHARING)
 
 #define _thread_offset_to_fcsr \
 	(___thread_t_callee_saved_OFFSET + ___callee_saved_t_fcsr_OFFSET)
@@ -100,7 +100,7 @@
 #define _thread_offset_to_fs11 \
 	(___thread_t_callee_saved_OFFSET + ___callee_saved_t_fs11_OFFSET)
 
-#endif /* defined(CONFIG_FLOAT) && defined(CONFIG_FP_SHARING) */
+#endif /* defined(CONFIG_FPU) && defined(CONFIG_FP_SHARING) */
 
 /* end - threads */
 

diff --git a/arch/x86/core/Kconfig.ia32 b/arch/x86/core/Kconfig.ia32
@@ -80,7 +80,7 @@ depends on CPU_HAS_FPU
 
 config SSE
 	bool "SSE registers"
-	depends on FLOAT
+	depends on FPU
 	help
 	  This option enables the use of SSE registers by threads.
 
@@ -100,7 +100,7 @@ config SSE_FP_MATH
 
 config EAGER_FP_SHARING
 	bool
-	depends on FLOAT
+	depends on FPU
 	depends on USERSPACE
 	default y if !X86_NO_LAZY_FP
 	help
@@ -110,12 +110,12 @@ config EAGER_FP_SHARING
 	  Mitigates CVE-2018-3665, but incurs a performance hit.
 
 	  For vulnerable systems that process sensitive information in the
-	  FPU register set, should be used any time CONFIG_FLOAT is
+	  FPU register set, should be used any time CONFIG_FPU is
 	  enabled, regardless if the FPU is used by one thread or multiple.
 
 config LAZY_FP_SHARING
 	bool
-	depends on FLOAT
+	depends on FPU
 	depends on !EAGER_FP_SHARING
 	depends on FP_SHARING
 	default y if X86_NO_LAZY_FP || !USERSPACE

diff --git a/arch/x86/core/ia32/crt0.S b/arch/x86/core/ia32/crt0.S
@@ -85,7 +85,7 @@ __csSet:
 #endif /* CONFIG_SET_GDT */
 
 
-#if !defined(CONFIG_FLOAT)
+#if !defined(CONFIG_FPU)
 	/*
 	 * Force an #NM exception for floating point instructions
 	 * since FP support hasn't been configured
@@ -126,7 +126,7 @@ __csSet:
 
   #endif /* CONFIG_SSE */
 
-#endif /* !CONFIG_FLOAT */
+#endif /* !CONFIG_FPU */
 
 	/*
 	 * Set the stack pointer to the area used for the interrupt stack.