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Commits on Feb 18, 2016

• SCOPE: bugfix AXI transfer settings

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  HrRossi

  committed
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Commits on Oct 26, 2015

• FPGA: removing unmaintained 'daisy' code

  

  Iztok Jeras

  committed
  a36279e

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Commits on Sep 19, 2015

• FPGA: scope arm-keep signal was missing a proper reset

  

  Iztok Jeras

  committed
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Commits on Sep 7, 2015

• FPGA: added basic PWM code and bench

  

  Iztok Jeras

  committed
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Commits on Sep 3, 2015

• Revert "FPGA-RTL: enable clearing 'arm' bit in the 'control' register, by writing 0 into it"

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  Iztok Jeras

  committed
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Commits on Aug 17, 2015

• FPGA-RTL: LED[0] is now a notmal software controlable output

  

  Iztok Jeras

  committed
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Commits on Jul 23, 2015

• attempt to connect XADC to AXI interconnect

  

  Iztok Jeras

  committed
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Commits on Jul 22, 2015

• FPGA: removing unused RTL file red_pitaya_analog.v

  

  Iztok Jeras

  committed
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Commits on Jul 6, 2015

• whitespace cleanup

  

  Iztok Jeras

  committed
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• Makefile: change zip file name

  

  Iztok Jeras

  committed
  13d6ffb

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Commits on Jul 2, 2015

• FPGA-RTL: update to signal generator

  

  Iztok Jeras

  committed
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Commits on Jun 29, 2015

• FPGA-RTL: fixed generator issue which could lead to slightly wrong frequencies

  

  Iztok Jeras

  committed
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• FPGA-RTL: attempt to fix generator regression

  

  Iztok Jeras

  committed
  6c5de02

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Commits on Jun 12, 2015

• FPGA-RTL: enable clearing 'arm' bit in the 'control' register, by writing 0 into it

  

  Iztok Jeras

  committed
  1f01489

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Commits on Jun 9, 2015

• FPGA-RTL: timing fixes proprosed by Pavel Demin

  

  Iztok Jeras

  committed
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Commits on Jun 1, 2015

• FPGA-RTL: attempt to fix a timing issue

  

  Iztok Jeras

  committed
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Commits on May 27, 2015

• Merge remote-tracking branch 'remotes/origin/master' into devel_fpga_2015_1

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  Iztok Jeras

  committed
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Commits on May 13, 2015

• FPGA: moving fpga files up in the hierarchy

  jeras

  committed
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