arm: use BASEPRI_MAX instead of BASEPRI to mask interrupts

When locking interrupt in a critical session, it is
safer to do MSR BASEPRI_MAX instead of BASEPRI. The
rationale is that when writing to BASEPRI_MAX, the
writing is conditional, and is only applied if the
change is to a higher priority level. This commit
replaces BASEPRI with BASEPRI_MAX in operations that
aim to lock some specific interrupts:
- irq_lock()
- masking out PendSV
So, for example, it is not possible to actually
unmask any interrupts by doing an irq_lock operation.
The commit does not introduce behavioral changes.
However, it makes irq_lock() more robust against
future changes to the IRQ locking mechanism.

Signed-off-by: Ioannis Glaropoulos <[email protected]>

arch/arm/core/aarch32/swap_helper.S

@@ -130,7 +130,7 @@ out_fp_endif:
     cpsid i
 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
     movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
-    msr BASEPRI, r0
+    msr BASEPRI_MAX, r0
     isb /* Make the effect of disabling interrupts be realized immediately */
 #elif defined(CONFIG_ARMV7_R)
     /*

arch/arm/core/aarch32/userspace.S

@@ -192,7 +192,7 @@ SECTION_FUNC(TEXT,z_arm_userspace_enter)
 
     /* Lock PendSV while reprogramming PSP and PSPLIM */
     mov r0, #_EXC_PENDSV_PRIO_MASK
-    msr BASEPRI, r0
+    msr BASEPRI_MAX, r0
     isb
 
     /* Set PSPLIM to guard the thread's user stack. */
@@ -456,7 +456,7 @@ dispatch_syscall:
 
     /* Lock PendSV while reprogramming PSP and PSPLIM */
     mov r3, #_EXC_PENDSV_PRIO_MASK
-    msr BASEPRI, r3
+    msr BASEPRI_MAX, r3
     isb
 
     /* Set PSPLIM to guard the thread's user stack. */

include/arch/arm/aarch32/asm_inline_gcc.h

@@ -56,7 +56,7 @@ static ALWAYS_INLINE unsigned int arch_irq_lock(void)
 	__asm__ volatile(
 		"mov %1, %2;"
 		"mrs %0, BASEPRI;"
-		"msr BASEPRI, %1;"
+		"msr BASEPRI_MAX, %1;"
 		"isb;"
 		: "=r"(key), "=r"(tmp)
 		: "i"(_EXC_IRQ_DEFAULT_PRIO)