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1. verilog verilog Public

   Yaklaşık 2500 satır markdown'dan oluşan bu eğitsel, herhangi bir donanım tanımlama dili bilgisi bulunmayan biri için 20 günlük bir çalışma ile tamamlanabilir halde, öz olarak işlenmiştir.

2. OpenLane OpenLane Public

   Forked from The-OpenROAD-Project/OpenLane

   OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

   Verilog

3. skywater-pdk skywater-pdk Public

   Forked from google/skywater-pdk

   Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

   Python

4. caravel caravel Public

   Forked from efabless/caravel

   Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

   Verilog

5. caravel_user_project caravel_user_project Public template

   Forked from efabless/caravel_user_project

   https://caravel-user-project.readthedocs.io

   Verilog