Adjusted idelay (errors on bus 3); reverted counter width; pipelined …

…Artix TB checker

src/FlashController.bsv

@@ -126,8 +126,8 @@ module mkFlashController#(
 
 	Vector#(NUM_BUSES, Reg#(ChipT)) wdataChip <- replicateM(mkReg(0, clocked_by clk0, reset_by rst0));
 	Vector#(NUM_BUSES, Reg#(Bit#(16))) wdataCnt <- replicateM(mkReg(0, clocked_by clk0, reset_by rst0));
-	Vector#(NUM_BUSES, Reg#(Bit#(8))) wdataCntSub <- replicateM(mkReg(0, clocked_by clk0, reset_by rst0));
-	Vector#(NUM_BUSES, Reg#(Bit#(8))) rdataCntSub <- replicateM(mkReg(0, clocked_by clk0, reset_by rst0));
+	Vector#(NUM_BUSES, Reg#(Bit#(16))) wdataCntSub <- replicateM(mkReg(0, clocked_by clk0, reset_by rst0));
+	Vector#(NUM_BUSES, Reg#(Bit#(16))) rdataCntSub <- replicateM(mkReg(0, clocked_by clk0, reset_by rst0));
 	Vector#(NUM_BUSES, Reg#(Bit#(128))) rdataAggrReg <- replicateM(mkReg(0, clocked_by clk0, reset_by rst0));
 	FIFO#(Tuple2#(TagT, StatusT)) ackStatusQ <- mkSizedFIFO(16, clocked_by clk0, reset_by rst0);
 

src/TODO

@@ -1,30 +1,29 @@
-- Repackage data over Serial links
 
-- One read data buffer per bus, if no space, don't start read transfer (read may err out if not drained fast enough)
+/*** Pending Testing ***/
+- Handle status returning E1 on block erases (failed)
+
 
 
-- Timing and FIFO size adjustments; ECC fifos sizes and timing too conservative
+/*** To Do Features ***/
+- Repackage data over Serial links
+- Increase usable page size for metadata 
 - ECC can't correct flag handling
-- May need additional ECC decoders to max bandwidth
-- Possible issue: decodeInQ is full if there are too many errors. This could occur after many sequential reads as the buffer slowly fills due to slow ECC.
-- Handle status returning E1 on block erases (failed)
 
+
+/*** Optimizations ***/
+- Optimization: Scheduler should not scheudle readback if no space is available in the read buffer (or decodeInQ)
+- Timing and FIFO size adjustments; ECC fifos sizes and timing too conservative
+- May need additional ECC decoders to max bandwidth
 - SB optimization: prioritize read command issuing
-- SB resource reduction: get rid of BRAM FIFO on chipQs
 - Adjust status polling freq
 - Sim test erases, r/w/e mixed 
 
 
-
-/*** May not be needed ***/
-- Read calibration for each chip. For now calibrate a single chip and use that calib value for the entire bus [ok here?]
-- DQ-DQS skew calibration [ok here?]
-- Remove DQS simulation delay in post implementation sim
-- IDELAY tap currently fixed in parameter. Need to make adjustable [don't need?]
-- delay adjustment for DQ line [don't need?]
-
-
 /*** DONE ***/
+- Artix only TopTB pipelined checker [bitstream generated in TB PROJECT]
+- Bug fix: read-related data fifos (KQ, TQin) full and blocking reads causing bad data to be read
+- SB resource reduction: get rid of BRAM FIFO on chipQs
+- Possible issue: decodeInQ is full if there are too many errors. This could occur after many sequential reads as the buffer slowly fills due to slow ECC.
 - [irrelevant] Opt: If write data has not been received for the particular chip, SB should move onto next chip
 - FIX LATENCY COUNTER (keep two 64bit counters, one for lat one for bytes read)
 - Compile for 8 buses - does regfile have enough ports? No. We can either replicate for each bus or try to use arrays directly. Replicated.
@@ -63,6 +62,13 @@
 - UCF verification: double check wen_nclk pins
 - Output drive strength, slew rate (FPGA and NAND)? <- doesn't seem to be a problem
 
+//Didn't need
+- Read calibration for each chip. For now calibrate a single chip and use that calib value for the entire bus [ok here?]
+- DQ-DQS skew calibration [ok here?]
+- Remove DQS simulation delay in post implementation sim
+- IDELAY tap currently fixed in parameter. Need to make adjustable [don't need?]
+- delay adjustment for DQ line [don't need?]
+
 /*** Testing ***/
 - [OK] All buses
 - [OK] High toggle rate data

src/TopTB.bsv

@@ -181,7 +181,8 @@ function FlashCmd getNextCmd (TagT tag, Bit#(8) testSetSel, Bit#(16) cmdCnt);
 			op = ERASE_BLOCK;
 		end
 	end
-/*
+
+`ifndef NAND_SIM //if not simulating, then include tb for all buses
 	//sequential read, 4 buses
 	else if (testSetSel == 8'h07) begin
 		if (cmdCnt < fromInteger(numSeqBlks)) begin //issue 10k commands (~80MB)
@@ -361,7 +362,10 @@ function FlashCmd getNextCmd (TagT tag, Bit#(8) testSetSel, Bit#(16) cmdCnt);
 		blk = zeroExtend(cmdCnt[13:6]); //16k blocks is 14-bit cmdCnt
 		op = READ_PAGE;
 	end
-*/
+
+`endif //ifndef NAND_SIM
+
+
    //Sim: 2 writes, 2 reads same chip/bus
 	else if (testSetSel == 8'hFF) begin
 		bus = 0;
@@ -426,9 +430,6 @@ module mkTopTB#(
 	Reg#(Bit#(16)) wdataCnt <- mkReg(0, clocked_by clk0, reset_by rst0);
 	Reg#(Bit#(2)) wrState <- mkReg(0, clocked_by clk0, reset_by rst0);
 
-	FIFO#(Bit#(128)) rdata2check <- mkFIFO(clocked_by clk0, reset_by rst0);
-	FIFO#(FlashCmd) rcmd2check <- mkFIFO(clocked_by clk0, reset_by rst0);
-
 	Reg#(Bit#(64)) latencyCnt <- mkReg(0, clocked_by clk0, reset_by rst0);
 	Vector#(NUM_BUSES, Reg#(Bit#(64))) errCnt <- replicateM(mkReg(0, clocked_by clk0, reset_by rst0));
 	Reg#(Bit#(16)) cmdCnt <- mkReg(0, clocked_by clk0, reset_by rst0);
@@ -536,7 +537,7 @@ module mkTopTB#(
 		wrState <= 1;
 	endrule
 
-	//TODO: insert some delays to simulate PCIe delay
+	/*
 	Reg#(Bit#(32)) wrDelayCnt <- mkReg(50, clocked_by clk0, reset_by rst0);
 
 	rule doWriteDataReqDelay if (wrState == 1);
@@ -548,15 +549,15 @@ module mkTopTB#(
 			wrDelayCnt<=wrDelayCnt - 1;
 		end
 	endrule
+	*/
 
 	//Send write data slowly
-	rule doWriteDataSend if (wrState ==2);
+	rule doWriteDataSend if (wrState ==1);
 		if (wdataCnt < fromInteger(pageSizeUser/16)) begin
 			Bit#(128) wData = getDataHash(wdataCnt, tagCmd.page, 
 											tagCmd.block, tagCmd.chip, tagCmd.bus);
 			flashCtrl.user.writeWord(tuple2(wData, tagCmd.tag));
 			wdataCnt <= wdataCnt + 1;
-			wrState <= 1;
 			$display("@%t\t%m: tb sent write data [%d]: %x", $time, wdataCnt, wData);
 		end
 		else begin
@@ -568,23 +569,77 @@ module mkTopTB#(
 	endrule
 
 	//Pipelined to reduce critical path
+	/*
+	//FIXME: testing read slowly
+	Reg#(Tuple2#(Bit#(128), TagT)) taggedRDataR <- mkRegU(clocked_by clk0, reset_by rst0);
+	Reg#(Bit#(4)) readState <- mkReg(0, clocked_by clk0, reset_by rst0);
+	Reg#(Bit#(32)) readWait <- mkReg(10000, clocked_by clk0, reset_by rst0);
+	rule doReadDataAccept if (readState==0);
+		let taggedRData <- flashCtrl.user.readWord();
+		taggedRDataR <= taggedRData;
+		readState <= 1;
+	endrule
+
+	rule doReadWait if (readState==1);
+		if (readWait ==  0) begin
+			readState <= 2;
+			readWait <= 16;
+		end
+		else begin
+			readWait <= readWait - 1;
+		end
+	endrule
+
+
+	rule doReadDecode if (readState == 2);
+		let taggedRData = taggedRDataR;
+		Bit#(128) rdata = tpl_1(taggedRData);
+		//rDataDebug[i] <= rdata;
+		TagT rTag = tpl_2(taggedRData);
+		FlashCmd cmd = tagTable.sub(rTag);
+		//FlashCmd cmd = tagTable[rTag];
+		rdata2check.enq(rdata);
+		rcmd2check.enq(cmd);
+		readState <= 0;
+	endrule
+	*/
+
+	FIFO#(Bit#(128)) rdata2gold <- mkFIFO(clocked_by clk0, reset_by rst0);
+	FIFO#(Bit#(128)) rdata2check <- mkFIFO(clocked_by clk0, reset_by rst0);
+	FIFO#(Bit#(128)) wdata2check <- mkFIFO(clocked_by clk0, reset_by rst0);
+	FIFO#(FlashCmd) rcmd2gold <- mkFIFO(clocked_by clk0, reset_by rst0);
+	FIFO#(FlashCmd) rcmd2check <- mkFIFO(clocked_by clk0, reset_by rst0);
+
 	rule doReadData;
 		let taggedRData <- flashCtrl.user.readWord();
 		Bit#(128) rdata = tpl_1(taggedRData);
 		//rDataDebug[i] <= rdata;
 		TagT rTag = tpl_2(taggedRData);
 		FlashCmd cmd = tagTable.sub(rTag);
 		//FlashCmd cmd = tagTable[rTag];
+		rdata2gold.enq(rdata);
+		rcmd2gold.enq(cmd);
+	endrule
+
+	rule doReadDataGold;
+		FlashCmd cmd = rcmd2gold.first;
+		Bit#(128) rdata = rdata2gold.first;
+		rcmd2gold.deq();
+		rdata2gold.deq();
+		Bit#(128) wData = getDataHash(rdataCnt[cmd.tag], cmd.page, cmd.block, cmd.chip, cmd.bus);
 		rdata2check.enq(rdata);
+		wdata2check.enq(wData);
 		rcmd2check.enq(cmd);
 	endrule
 
+
 	rule doReadDataCheck;
 		FlashCmd cmd = rcmd2check.first;
 		Bit#(128) rdata = rdata2check.first;
-		rcmd2check.deq();
-		rdata2check.deq();
-		Bit#(128) wData = getDataHash(rdataCnt[cmd.tag], cmd.page, cmd.block, cmd.chip, cmd.bus);
+		Bit#(128) wData = wdata2check.first;
+		wdata2check.deq;
+		rdata2check.deq;
+		rcmd2check.deq;
 
 		//check
 		if (rdata != wData) begin

src/nand_phy_dqs_iob.v

@@ -6,7 +6,7 @@ module nand_phy_dqs_iob #
 	parameter DQS_NET_DELAY			  = 1.0, //TODO FUnctional simulation only!!
    parameter HIGH_PERFORMANCE_MODE = "TRUE",
    parameter IODELAY_GRP           = "IODELAY_NAND",
-	parameter IDELAY_TAP 			  = 16
+	parameter IDELAY_TAP 			  = 20
    )
   (
    input        clk0,