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Commits on Dec 12, 2014

• fixed bug with ECC ChienSearch count_error

  m-liu

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  99ba78c

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Commits on Nov 10, 2014

• controller type changes

  m-liu

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Commits on Sep 22, 2014

• Adjusted idelay (errors on bus 3); reverted counter width; pipelined Artix TB checker

  m-liu

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Commits on Sep 21, 2014

• Modified bus controller to wait on reads if no space is available in the buffer (i.e. if pcie or GTP is slow); expanded read related buffers; timing tweaks

  m-liu

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Commits on Sep 18, 2014

• Connected controller to aurora GTP; removed reset from virtex (bug);

  m-liu

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Commits on Sep 15, 2014

• small interface changes (for serial link integration)

  m-liu

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Commits on Sep 12, 2014

• Redesigned write buffering scheme - 2 page bufs per bus instead of 1 buf per chip

  m-liu

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• isolated and redefined flash interface; added write page buffers for each chip; separated TB

  m-liu

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Commits on Aug 23, 2014

• Expanded test set and chipscope; 8 buses working in hardware

  m-liu

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Commits on Aug 18, 2014

• SLC mapping and ifdefs added

  m-liu

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Commits on Aug 17, 2014

• fixed extra tag deq when command is invalid (causes test to not finish); added state to tell us when the test is done

  m-liu

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Commits on Aug 15, 2014

• Fixed tagFreeList fifo conflict that prevented rules from firing to capture data

  m-liu

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  b00684e

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• Added free tag list; fixed erase delay bug that was preventing parallel erases; added sequential r/w/e test cases; more chipscope probes and performance counters

  m-liu

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Commits on Aug 13, 2014

• ISE chipscope IP updates

  m-liu

  committed
  3d85e7d

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• separated out chipscope IP from phy; created srcs for vivado; compiles and works in vivado for 4 buses (so far)

  m-liu

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Commits on Aug 12, 2014

• removed old vivado project

  m-liu

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• removed chipscope icon for bscan1 (doesn't work)

  m-liu

  committed
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• Testbench improvements: issue sets of commands that can be scheduled in parallel; Use regfile for tag table; pipelined read checks

  m-liu

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Commits on Aug 11, 2014

• Scoreboard integrated; functional sim works, hw needs testing and timing/fifo adjustments

  m-liu

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Commits on Aug 7, 2014

• Added Scoreboard and Scoreboard testbench

  m-liu

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Commits on Aug 5, 2014

• Code restructure in Bus and Flash controller to interface with Scoreboard; compiles but untested

  m-liu

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Commits on Aug 4, 2014

• updated chipscope core with more depth, less control lines

  m-liu

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  7c9273f

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• Turned register ordering option off in Map

  m-liu

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  f912921

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• ECC decoder works in HW; most likely BRAM FIFO helped resolve issue - not sure; dirty commit, clean up pending

  m-liu

  committed
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Commits on Aug 3, 2014

• Integrated ECC RS decoder; fixed RS decoder pipeline bug on no error blocks; functional sim passes

  m-liu

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Commits on Jul 30, 2014

• Integrated ECC encoder

  m-liu

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  1c5e919

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• Clean up chipscope files

  m-liu

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Commits on Jul 28, 2014

• Fixed rlat bug: reg stage mismatch between rdata and calib data

  m-liu

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• added second chipscope icon core; added a layer of sync regs to dq calib regs for timing

  m-liu

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Commits on Jul 25, 2014

• expanded design to 8 buses; created shared WEN_NCLK module per chipbus; pulled out chipscope to top level; PENDING HARDWARE VERIFICATION

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Commits on Jul 18, 2014

• increased chipscope depth

  m-liu

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• Can now issue commands through chipscope VIO; make sim now compiles sim version

  m-liu

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Commits on Jul 17, 2014

• added VIO debug port; cleaned up ILA debug interface

  m-liu

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  1f69266

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• updated chipscope icon core

  m-liu

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• chipscope vio ip generated

  m-liu

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