GPGPU microprocessor architecture

Allo: A Programming Model for Composable Accelerator Design

ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen

A hardware synthesis framework with multi-level paradigm

Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.

GPU Accelerated t-SNE for CUDA with Python bindings

A Manual on Surviving in CS of NWPU

Our repository for NSCSCC

MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design

An DSP library written in Python for performing HRTFs

Basic Machine Learning and Deep Learning

PointPWC-Net is a deep coarse-to-fine network designed for 3D scene flow estimation from 3D point clouds.

A PyTorch implementation of "ContourNet: Taking a Further Step toward Accurate Arbitrary-shaped Scene Text Detection" (CVPR2020)

The official code of Linguistic More: Taking a Further Step toward Efficient and Accurate Scene Text Recognition (IJCAI2023)

Video-LLaMA: An Instruction-tuned Audio-Visual Language Model for Video Understanding

EVFlowNet in pytorch

Project Repo for the Simulator Independent Coverage Research

ChampSim is an open-source trace based simulator maintained at Texas A&M University and through the support of the computer architecture community.

Verilator open-source SystemVerilog simulator and lint system

A Modular Open-Source Hardware Fuzzing Framework

A Chisel RTL generator for network-on-chip interconnects

A Formal Verification Framework for Chisel

A template project for beginning new Chisel work

Chisel: A Modern Hardware Design Language